NXP Semiconductors MKL28T7_CORE0 2024.06.02 MKL28T7_CORE0 Freescale Microcontroller CM0PLUS r0p0 little 2 false 8 32 ADC0 Analog-to-Digital Converter ADC0 0x0 0x0 0x70 registers n ADC0 25 CFG1 ADC Configuration Register 1 0x8 32 read-write n 0x0 0x0 ADICLK Input Clock Select 0 2 read-write 00 Bus clock #00 01 Bus clock divided by 2(BUSCLK/2) #01 10 Alternate clock (ALTCLK) #10 11 Asynchronous clock (ADACK) #11 ADIV Clock Divide Select 5 2 read-write 00 The divide ratio is 1 and the clock rate is input clock. #00 01 The divide ratio is 2 and the clock rate is (input clock)/2. #01 10 The divide ratio is 4 and the clock rate is (input clock)/4. #10 11 The divide ratio is 8 and the clock rate is (input clock)/8. #11 ADLPC Low-Power Configuration 7 1 read-write 0 Normal power configuration. #0 1 Low-power configuration. The power is reduced at the expense of maximum clock speed. #1 ADLSMP Sample Time Configuration 4 1 read-write 0 Short sample time. #0 1 Long sample time. #1 MODE Conversion mode selection 2 2 read-write 00 When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output. #00 01 When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output. #01 10 When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output #10 11 When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output #11 CFG2 ADC Configuration Register 2 0xC 32 read-write n 0x0 0x0 ADACKEN Asynchronous Clock Output Enable 3 1 read-write 0 Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active. #0 1 Asynchronous clock and clock output is enabled regardless of the state of the ADC. #1 ADHSC High-Speed Configuration 2 1 read-write 0 Normal conversion sequence selected. #0 1 High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time. #1 ADLSTS Long Sample Time Select 0 2 read-write 00 Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total. #00 01 12 extra ADCK cycles; 16 ADCK cycles total sample time. #01 10 6 extra ADCK cycles; 10 ADCK cycles total sample time. #10 11 2 extra ADCK cycles; 6 ADCK cycles total sample time. #11 MUXSEL ADC Mux Select 4 1 read-write 0 ADxxa channels are selected. #0 1 ADxxb channels are selected. #1 CLM0 ADC Minus-Side General Calibration Value Register 0x6C 32 read-write n 0x0 0x0 CLM0 Calibration Value 0 6 read-write CLM1 ADC Minus-Side General Calibration Value Register 0x68 32 read-write n 0x0 0x0 CLM1 Calibration Value 0 7 read-write CLM2 ADC Minus-Side General Calibration Value Register 0x64 32 read-write n 0x0 0x0 CLM2 Calibration Value 0 8 read-write CLM3 ADC Minus-Side General Calibration Value Register 0x60 32 read-write n 0x0 0x0 CLM3 Calibration Value 0 9 read-write CLM4 ADC Minus-Side General Calibration Value Register 0x5C 32 read-write n 0x0 0x0 CLM4 Calibration Value 0 10 read-write CLMD ADC Minus-Side General Calibration Value Register 0x54 32 read-write n 0x0 0x0 CLMD Calibration Value 0 6 read-write CLMS ADC Minus-Side General Calibration Value Register 0x58 32 read-write n 0x0 0x0 CLMS Calibration Value 0 6 read-write CLP0 ADC Plus-Side General Calibration Value Register 0x4C 32 read-write n 0x0 0x0 CLP0 Calibration Value 0 6 read-write CLP1 ADC Plus-Side General Calibration Value Register 0x48 32 read-write n 0x0 0x0 CLP1 Calibration Value 0 7 read-write CLP2 ADC Plus-Side General Calibration Value Register 0x44 32 read-write n 0x0 0x0 CLP2 Calibration Value 0 8 read-write CLP3 ADC Plus-Side General Calibration Value Register 0x40 32 read-write n 0x0 0x0 CLP3 Calibration Value 0 9 read-write CLP4 ADC Plus-Side General Calibration Value Register 0x3C 32 read-write n 0x0 0x0 CLP4 Calibration Value 0 10 read-write CLPD ADC Plus-Side General Calibration Value Register 0x34 32 read-write n 0x0 0x0 CLPD Calibration Value 0 6 read-write CLPS ADC Plus-Side General Calibration Value Register 0x38 32 read-write n 0x0 0x0 CLPS Calibration Value 0 6 read-write CV1 Compare Value Registers 0x30 32 read-write n 0x0 0x0 CV Compare Value. 0 16 read-write CV2 Compare Value Registers 0x4C 32 read-write n 0x0 0x0 CV Compare Value. 0 16 read-write MG ADC Minus-Side Gain Register 0x30 32 read-write n 0x0 0x0 MG Minus-Side Gain 0 16 read-write OFS ADC Offset Correction Register 0x28 32 read-write n 0x0 0x0 OFS Offset Error Correction Value 0 16 read-write PG ADC Plus-Side Gain Register 0x2C 32 read-write n 0x0 0x0 PG Plus-Side Gain 0 16 read-write RA ADC Data Result Register 0x20 32 read-only n 0x0 0x0 D Data result 0 16 read-only RB ADC Data Result Register 0x34 32 read-only n 0x0 0x0 D Data result 0 16 read-only SC1A ADC Status and Control Registers 1 0x0 32 read-write n 0x0 0x0 ADCH Input channel select 0 5 read-write 00000 When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. #00000 00001 When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. #00001 00010 When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. #00010 00011 When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. #00011 00100 When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. #00100 00101 When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. #00101 00110 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. #00110 00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. #00111 01000 When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. #01000 01001 When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. #01001 01010 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. #01010 01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. #01011 01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. #01100 01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. #01101 01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. #01110 01111 When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. #01111 10000 When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. #10000 10001 When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. #10001 10010 When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. #10010 10011 When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. #10011 10100 When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. #10100 10101 When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. #10101 10110 When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. #10110 10111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. #10111 11010 When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input. #11010 11011 When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. #11011 11101 When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL]. #11101 11110 When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL]. #11110 11111 Module is disabled. #11111 AIEN Interrupt Enable 6 1 read-write 0 Conversion complete interrupt is disabled. #0 1 Conversion complete interrupt is enabled. #1 COCO Conversion Complete Flag 7 1 read-only 0 Conversion is not completed. #0 1 Conversion is completed. #1 DIFF Differential Mode Enable 5 1 read-write 0 Single-ended conversions and input channels are selected. #0 1 Differential conversions and input channels are selected. #1 SC1B ADC Status and Control Registers 1 0x4 32 read-write n 0x0 0x0 ADCH Input channel select 0 5 read-write 00000 When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. #00000 00001 When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. #00001 00010 When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. #00010 00011 When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. #00011 00100 When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. #00100 00101 When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. #00101 00110 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. #00110 00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. #00111 01000 When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. #01000 01001 When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. #01001 01010 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. #01010 01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. #01011 01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. #01100 01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. #01101 01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. #01110 01111 When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. #01111 10000 When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. #10000 10001 When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. #10001 10010 When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. #10010 10011 When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. #10011 10100 When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. #10100 10101 When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. #10101 10110 When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. #10110 10111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. #10111 11010 When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input. #11010 11011 When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. #11011 11101 When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL]. #11101 11110 When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL]. #11110 11111 Module is disabled. #11111 AIEN Interrupt Enable 6 1 read-write 0 Conversion complete interrupt is disabled. #0 1 Conversion complete interrupt is enabled. #1 COCO Conversion Complete Flag 7 1 read-only 0 Conversion is not completed. #0 1 Conversion is completed. #1 DIFF Differential Mode Enable 5 1 read-write 0 Single-ended conversions and input channels are selected. #0 1 Differential conversions and input channels are selected. #1 SC2 Status and Control Register 2 0x20 32 read-write n 0x0 0x0 ACFE Compare Function Enable 5 1 read-write 0 Compare function disabled. #0 1 Compare function enabled. #1 ACFGT Compare Function Greater Than Enable 4 1 read-write 0 Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2. #0 1 Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2. #1 ACREN Compare Function Range Enable 3 1 read-write 0 Range function disabled. Only CV1 is compared. #0 1 Range function enabled. Both CV1 and CV2 are compared. #1 ADACT Conversion Active 7 1 read-only 0 Conversion not in progress. #0 1 Conversion in progress. #1 ADTRG Conversion Trigger Select 6 1 read-write 0 Software trigger selected. #0 1 Hardware trigger selected. #1 DMAEN DMA Enable 2 1 read-write 0 DMA is disabled. #0 1 DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted. #1 REFSEL Voltage Reference Selection 0 2 read-write 00 Default voltage reference pin pair, that is, external pins VREFH and VREFL #00 01 Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU #01 SC3 Status and Control Register 3 0x24 32 read-write n 0x0 0x0 ADCO Continuous Conversion Enable 3 1 read-write 0 One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. #0 1 Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. #1 AVGE Hardware Average Enable 2 1 read-write 0 Hardware average function disabled. #0 1 Hardware average function enabled. #1 AVGS Hardware Average Select 0 2 read-write 00 4 samples averaged. #00 01 8 samples averaged. #01 10 16 samples averaged. #10 11 32 samples averaged. #11 CAL Calibration 7 1 read-write CALF Calibration Failed Flag 6 1 read-write 0 Calibration completed normally. #0 1 Calibration failed. ADC accuracy specifications are not guaranteed. #1 ASMC ASMC (Auxiliary System Mode Control) Module ASMC 0x0 0x0 0x18 registers n PMCTRL Power Mode Control register 0xC 32 read-write n 0x0 0x0 RUNM Run Mode Control 5 2 read-write 00 Normal Run mode (RUN) #00 10 Very-Low-Power Run mode (VLPR) #10 11 High Speed Run mode (HSRUN) #11 STOPM Stop Mode Control 0 3 read-write 000 Normal Stop (STOP) #000 010 Very-Low-Power Stop (VLPS) #010 011 Low-Leakage Stop (LLSx) #011 100 Very-Low-Leakage Stop (VLLSx) #100 110 Reseved #110 PMPROT Power Mode Protection register 0x8 32 read-write n 0x0 0x0 AHSRUN Allow High Speed Run mode 7 1 read-write 0 HSRUN is not allowed #0 1 HSRUN is allowed #1 ALLS Allow Low-Leakage Stop Mode 3 1 read-write 0 Any LLSx mode is not allowed #0 1 Any LLSx mode is allowed #1 AVLLS Allow Very-Low-Leakage Stop Mode 1 1 read-write 0 Any VLLSx mode is not allowed #0 1 Any VLLSx mode is allowed #1 AVLP Allow Very-Low-Power Modes 5 1 read-write 0 VLPR, VLPW, and VLPS are not allowed. #0 1 VLPR, VLPW, and VLPS are allowed. #1 PMSTAT Power Mode Status register 0x14 32 read-only n 0x0 0x0 PMSTAT Power Mode Status 0 8 read-only SRS System Reset Status Register 0x0 32 read-only n 0x0 0x0 LOCKUP Core 1 Lockup 9 1 read-only 0 Reset not caused by core LOCKUP event #0 1 Reset caused by core LOCKUP event #1 POR Power-On Reset 7 1 read-only 0 Reset not caused by POR #0 1 Reset caused by POR #1 RES Chip Reset not POR 6 1 read-only 0 Chip Reset did not occur #0 1 Chip Reset caused by a source other than POR occured #1 SACKERR Stop Mode Acknowledge Error Reset 12 1 read-only 0 Reset not caused by peripheral failure to acknowledge attempt to enter stop mode #0 1 Reset caused by peripheral failure to acknowledge attempt to enter stop mode #1 SW Software 10 1 read-only 0 Reset not caused by software setting of SYSRESETREQ bit #0 1 Reset caused by software setting of SYSRESETREQ bit #1 WAKEUP Low Leakage Wakeup Reset 0 1 read-only 0 Reset not caused by LLWU module wakeup source #0 1 Reset caused by LLWU module wakeup source #1 WDOG1 Watchdog 5 1 read-only 0 Reset not caused by watchdog timeout #0 1 Reset caused by watchdog timeout #1 STOPCTRL Stop Control Register 0x10 32 read-write n 0x0 0x0 PSTOPO Partial Stop Option 6 2 read-write 00 STOP - Normal Stop mode #00 01 PSTOP1 - Partial Stop with both system and bus clocks disabled #01 10 PSTOP2 - Partial Stop with system clock disabled and bus clock enabled #10 CAU0 Memory Mapped Cryptographic Acceleration Unit (MMCAU) CAU0 0x0 0x0 0xB6C registers n CAU_ADR_CA0 General Purpose Register 0 - Add to register command 0x8C8 32 write-only n 0x0 0x0 CA0 CA0 0 32 write-only CAU_ADR_CA1 General Purpose Register 1 - Add to register command 0x8CC 32 write-only n 0x0 0x0 CA1 CA1 0 32 write-only CAU_ADR_CA2 General Purpose Register 2 - Add to register command 0x8D0 32 write-only n 0x0 0x0 CA2 CA2 0 32 write-only CAU_ADR_CA3 General Purpose Register 3 - Add to register command 0x8D4 32 write-only n 0x0 0x0 CA3 CA3 0 32 write-only CAU_ADR_CA4 General Purpose Register 4 - Add to register command 0x8D8 32 write-only n 0x0 0x0 CA4 CA4 0 32 write-only CAU_ADR_CA5 General Purpose Register 5 - Add to register command 0x8DC 32 write-only n 0x0 0x0 CA5 CA5 0 32 write-only CAU_ADR_CA6 General Purpose Register 6 - Add to register command 0x8E0 32 write-only n 0x0 0x0 CA6 CA6 0 32 write-only CAU_ADR_CA7 General Purpose Register 7 - Add to register command 0x8E4 32 write-only n 0x0 0x0 CA7 CA7 0 32 write-only CAU_ADR_CA8 General Purpose Register 8 - Add to register command 0x8E8 32 write-only n 0x0 0x0 CA8 CA8 0 32 write-only CAU_ADR_CAA Accumulator register - Add to register command 0x8C4 32 write-only n 0x0 0x0 ACC ACC 0 32 write-only CAU_ADR_CASR Status register - Add Register command 0x8C0 32 write-only n 0x0 0x0 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 CAU_AESC_CA0 General Purpose Register 0 - AES Column Operation command 0xB08 32 write-only n 0x0 0x0 CA0 CA0 0 32 write-only CAU_AESC_CA1 General Purpose Register 1 - AES Column Operation command 0xB0C 32 write-only n 0x0 0x0 CA1 CA1 0 32 write-only CAU_AESC_CA2 General Purpose Register 2 - AES Column Operation command 0xB10 32 write-only n 0x0 0x0 CA2 CA2 0 32 write-only CAU_AESC_CA3 General Purpose Register 3 - AES Column Operation command 0xB14 32 write-only n 0x0 0x0 CA3 CA3 0 32 write-only CAU_AESC_CA4 General Purpose Register 4 - AES Column Operation command 0xB18 32 write-only n 0x0 0x0 CA4 CA4 0 32 write-only CAU_AESC_CA5 General Purpose Register 5 - AES Column Operation command 0xB1C 32 write-only n 0x0 0x0 CA5 CA5 0 32 write-only CAU_AESC_CA6 General Purpose Register 6 - AES Column Operation command 0xB20 32 write-only n 0x0 0x0 CA6 CA6 0 32 write-only CAU_AESC_CA7 General Purpose Register 7 - AES Column Operation command 0xB24 32 write-only n 0x0 0x0 CA7 CA7 0 32 write-only CAU_AESC_CA8 General Purpose Register 8 - AES Column Operation command 0xB28 32 write-only n 0x0 0x0 CA8 CA8 0 32 write-only CAU_AESC_CAA Accumulator register - AES Column Operation command 0xB04 32 write-only n 0x0 0x0 ACC ACC 0 32 write-only CAU_AESC_CASR Status register - AES Column Operation command 0xB00 32 write-only n 0x0 0x0 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 CAU_AESIC_CA0 General Purpose Register 0 - AES Inverse Column Operation command 0xB48 32 write-only n 0x0 0x0 CA0 CA0 0 32 write-only CAU_AESIC_CA1 General Purpose Register 1 - AES Inverse Column Operation command 0xB4C 32 write-only n 0x0 0x0 CA1 CA1 0 32 write-only CAU_AESIC_CA2 General Purpose Register 2 - AES Inverse Column Operation command 0xB50 32 write-only n 0x0 0x0 CA2 CA2 0 32 write-only CAU_AESIC_CA3 General Purpose Register 3 - AES Inverse Column Operation command 0xB54 32 write-only n 0x0 0x0 CA3 CA3 0 32 write-only CAU_AESIC_CA4 General Purpose Register 4 - AES Inverse Column Operation command 0xB58 32 write-only n 0x0 0x0 CA4 CA4 0 32 write-only CAU_AESIC_CA5 General Purpose Register 5 - AES Inverse Column Operation command 0xB5C 32 write-only n 0x0 0x0 CA5 CA5 0 32 write-only CAU_AESIC_CA6 General Purpose Register 6 - AES Inverse Column Operation command 0xB60 32 write-only n 0x0 0x0 CA6 CA6 0 32 write-only CAU_AESIC_CA7 General Purpose Register 7 - AES Inverse Column Operation command 0xB64 32 write-only n 0x0 0x0 CA7 CA7 0 32 write-only CAU_AESIC_CA8 General Purpose Register 8 - AES Inverse Column Operation command 0xB68 32 write-only n 0x0 0x0 CA8 CA8 0 32 write-only CAU_AESIC_CAA Accumulator register - AES Inverse Column Operation command 0xB44 32 write-only n 0x0 0x0 ACC ACC 0 32 write-only CAU_AESIC_CASR Status register - AES Inverse Column Operation command 0xB40 32 write-only n 0x0 0x0 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 CAU_DIRECT0 Direct access register 0 0x0 32 write-only n 0x0 0x0 CAU_DIRECT0 Direct register 0 0 32 write-only CAU_DIRECT1 Direct access register 1 0x4 32 write-only n 0x0 0x0 CAU_DIRECT1 Direct register 1 0 32 write-only CAU_DIRECT10 Direct access register 10 0x28 32 write-only n 0x0 0x0 CAU_DIRECT10 Direct register 10 0 32 write-only CAU_DIRECT11 Direct access register 11 0x2C 32 write-only n 0x0 0x0 CAU_DIRECT11 Direct register 11 0 32 write-only CAU_DIRECT12 Direct access register 12 0x30 32 write-only n 0x0 0x0 CAU_DIRECT12 Direct register 12 0 32 write-only CAU_DIRECT13 Direct access register 13 0x34 32 write-only n 0x0 0x0 CAU_DIRECT13 Direct register 13 0 32 write-only CAU_DIRECT14 Direct access register 14 0x38 32 write-only n 0x0 0x0 CAU_DIRECT14 Direct register 14 0 32 write-only CAU_DIRECT15 Direct access register 15 0x3C 32 write-only n 0x0 0x0 CAU_DIRECT15 Direct register 15 0 32 write-only CAU_DIRECT2 Direct access register 2 0x8 32 write-only n 0x0 0x0 CAU_DIRECT2 Direct register 2 0 32 write-only CAU_DIRECT3 Direct access register 3 0xC 32 write-only n 0x0 0x0 CAU_DIRECT3 Direct register 3 0 32 write-only CAU_DIRECT4 Direct access register 4 0x10 32 write-only n 0x0 0x0 CAU_DIRECT4 Direct register 4 0 32 write-only CAU_DIRECT5 Direct access register 5 0x14 32 write-only n 0x0 0x0 CAU_DIRECT5 Direct register 5 0 32 write-only CAU_DIRECT6 Direct access register 6 0x18 32 write-only n 0x0 0x0 CAU_DIRECT6 Direct register 6 0 32 write-only CAU_DIRECT7 Direct access register 7 0x1C 32 write-only n 0x0 0x0 CAU_DIRECT7 Direct register 7 0 32 write-only CAU_DIRECT8 Direct access register 8 0x20 32 write-only n 0x0 0x0 CAU_DIRECT8 Direct register 8 0 32 write-only CAU_DIRECT9 Direct access register 9 0x24 32 write-only n 0x0 0x0 CAU_DIRECT9 Direct register 9 0 32 write-only CAU_LDR_CA0 General Purpose Register 0 - Load Register command 0x848 32 write-only n 0x0 0x0 CA0 CA0 0 32 write-only CAU_LDR_CA1 General Purpose Register 1 - Load Register command 0x84C 32 write-only n 0x0 0x0 CA1 CA1 0 32 write-only CAU_LDR_CA2 General Purpose Register 2 - Load Register command 0x850 32 write-only n 0x0 0x0 CA2 CA2 0 32 write-only CAU_LDR_CA3 General Purpose Register 3 - Load Register command 0x854 32 write-only n 0x0 0x0 CA3 CA3 0 32 write-only CAU_LDR_CA4 General Purpose Register 4 - Load Register command 0x858 32 write-only n 0x0 0x0 CA4 CA4 0 32 write-only CAU_LDR_CA5 General Purpose Register 5 - Load Register command 0x85C 32 write-only n 0x0 0x0 CA5 CA5 0 32 write-only CAU_LDR_CA6 General Purpose Register 6 - Load Register command 0x860 32 write-only n 0x0 0x0 CA6 CA6 0 32 write-only CAU_LDR_CA7 General Purpose Register 7 - Load Register command 0x864 32 write-only n 0x0 0x0 CA7 CA7 0 32 write-only CAU_LDR_CA8 General Purpose Register 8 - Load Register command 0x868 32 write-only n 0x0 0x0 CA8 CA8 0 32 write-only CAU_LDR_CAA Accumulator register - Load Register command 0x844 32 write-only n 0x0 0x0 ACC ACC 0 32 write-only CAU_LDR_CASR Status register - Load Register command 0x840 32 write-only n 0x0 0x0 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 CAU_RADR_CA0 General Purpose Register 0 - Reverse and Add to Register command 0x908 32 write-only n 0x0 0x0 CA0 CA0 0 32 write-only CAU_RADR_CA1 General Purpose Register 1 - Reverse and Add to Register command 0x90C 32 write-only n 0x0 0x0 CA1 CA1 0 32 write-only CAU_RADR_CA2 General Purpose Register 2 - Reverse and Add to Register command 0x910 32 write-only n 0x0 0x0 CA2 CA2 0 32 write-only CAU_RADR_CA3 General Purpose Register 3 - Reverse and Add to Register command 0x914 32 write-only n 0x0 0x0 CA3 CA3 0 32 write-only CAU_RADR_CA4 General Purpose Register 4 - Reverse and Add to Register command 0x918 32 write-only n 0x0 0x0 CA4 CA4 0 32 write-only CAU_RADR_CA5 General Purpose Register 5 - Reverse and Add to Register command 0x91C 32 write-only n 0x0 0x0 CA5 CA5 0 32 write-only CAU_RADR_CA6 General Purpose Register 6 - Reverse and Add to Register command 0x920 32 write-only n 0x0 0x0 CA6 CA6 0 32 write-only CAU_RADR_CA7 General Purpose Register 7 - Reverse and Add to Register command 0x924 32 write-only n 0x0 0x0 CA7 CA7 0 32 write-only CAU_RADR_CA8 General Purpose Register 8 - Reverse and Add to Register command 0x928 32 write-only n 0x0 0x0 CA8 CA8 0 32 write-only CAU_RADR_CAA Accumulator register - Reverse and Add to Register command 0x904 32 write-only n 0x0 0x0 ACC ACC 0 32 write-only CAU_RADR_CASR Status register - Reverse and Add to Register command 0x900 32 write-only n 0x0 0x0 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 CAU_ROTL_CA0 General Purpose Register 0 - Rotate Left command 0x9C8 32 write-only n 0x0 0x0 CA0 CA0 0 32 write-only CAU_ROTL_CA1 General Purpose Register 1 - Rotate Left command 0x9CC 32 write-only n 0x0 0x0 CA1 CA1 0 32 write-only CAU_ROTL_CA2 General Purpose Register 2 - Rotate Left command 0x9D0 32 write-only n 0x0 0x0 CA2 CA2 0 32 write-only CAU_ROTL_CA3 General Purpose Register 3 - Rotate Left command 0x9D4 32 write-only n 0x0 0x0 CA3 CA3 0 32 write-only CAU_ROTL_CA4 General Purpose Register 4 - Rotate Left command 0x9D8 32 write-only n 0x0 0x0 CA4 CA4 0 32 write-only CAU_ROTL_CA5 General Purpose Register 5 - Rotate Left command 0x9DC 32 write-only n 0x0 0x0 CA5 CA5 0 32 write-only CAU_ROTL_CA6 General Purpose Register 6 - Rotate Left command 0x9E0 32 write-only n 0x0 0x0 CA6 CA6 0 32 write-only CAU_ROTL_CA7 General Purpose Register 7 - Rotate Left command 0x9E4 32 write-only n 0x0 0x0 CA7 CA7 0 32 write-only CAU_ROTL_CA8 General Purpose Register 8 - Rotate Left command 0x9E8 32 write-only n 0x0 0x0 CA8 CA8 0 32 write-only CAU_ROTL_CAA Accumulator register - Rotate Left command 0x9C4 32 write-only n 0x0 0x0 ACC ACC 0 32 write-only CAU_ROTL_CASR Status register - Rotate Left command 0x9C0 32 write-only n 0x0 0x0 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 CAU_STR_CA0 General Purpose Register 0 - Store Register command 0x888 32 read-only n 0x0 0x0 CA0 CA0 0 32 read-only CAU_STR_CA1 General Purpose Register 1 - Store Register command 0x88C 32 read-only n 0x0 0x0 CA1 CA1 0 32 read-only CAU_STR_CA2 General Purpose Register 2 - Store Register command 0x890 32 read-only n 0x0 0x0 CA2 CA2 0 32 read-only CAU_STR_CA3 General Purpose Register 3 - Store Register command 0x894 32 read-only n 0x0 0x0 CA3 CA3 0 32 read-only CAU_STR_CA4 General Purpose Register 4 - Store Register command 0x898 32 read-only n 0x0 0x0 CA4 CA4 0 32 read-only CAU_STR_CA5 General Purpose Register 5 - Store Register command 0x89C 32 read-only n 0x0 0x0 CA5 CA5 0 32 read-only CAU_STR_CA6 General Purpose Register 6 - Store Register command 0x8A0 32 read-only n 0x0 0x0 CA6 CA6 0 32 read-only CAU_STR_CA7 General Purpose Register 7 - Store Register command 0x8A4 32 read-only n 0x0 0x0 CA7 CA7 0 32 read-only CAU_STR_CA8 General Purpose Register 8 - Store Register command 0x8A8 32 read-only n 0x0 0x0 CA8 CA8 0 32 read-only CAU_STR_CAA Accumulator register - Store Register command 0x884 32 read-only n 0x0 0x0 ACC ACC 0 32 read-only CAU_STR_CASR Status register - Store Register command 0x880 32 read-only n 0x0 0x0 DPE no description available 1 1 read-only 0 No error detected #0 1 DES key parity error detected #1 IC no description available 0 1 read-only 0 No illegal commands issued #0 1 Illegal command issued #1 VER CAU version 28 4 read-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 CAU_XOR_CA0 General Purpose Register 0 - Exclusive Or command 0x988 32 write-only n 0x0 0x0 CA0 CA0 0 32 write-only CAU_XOR_CA1 General Purpose Register 1 - Exclusive Or command 0x98C 32 write-only n 0x0 0x0 CA1 CA1 0 32 write-only CAU_XOR_CA2 General Purpose Register 2 - Exclusive Or command 0x990 32 write-only n 0x0 0x0 CA2 CA2 0 32 write-only CAU_XOR_CA3 General Purpose Register 3 - Exclusive Or command 0x994 32 write-only n 0x0 0x0 CA3 CA3 0 32 write-only CAU_XOR_CA4 General Purpose Register 4 - Exclusive Or command 0x998 32 write-only n 0x0 0x0 CA4 CA4 0 32 write-only CAU_XOR_CA5 General Purpose Register 5 - Exclusive Or command 0x99C 32 write-only n 0x0 0x0 CA5 CA5 0 32 write-only CAU_XOR_CA6 General Purpose Register 6 - Exclusive Or command 0x9A0 32 write-only n 0x0 0x0 CA6 CA6 0 32 write-only CAU_XOR_CA7 General Purpose Register 7 - Exclusive Or command 0x9A4 32 write-only n 0x0 0x0 CA7 CA7 0 32 write-only CAU_XOR_CA8 General Purpose Register 8 - Exclusive Or command 0x9A8 32 write-only n 0x0 0x0 CA8 CA8 0 32 write-only CAU_XOR_CAA Accumulator register - Exclusive Or command 0x984 32 write-only n 0x0 0x0 ACC ACC 0 32 write-only CAU_XOR_CASR Status register - Exclusive Or command 0x980 32 write-only n 0x0 0x0 DPE no description available 1 1 write-only 0 No error detected #0 1 DES key parity error detected #1 IC no description available 0 1 write-only 0 No illegal commands issued #0 1 Illegal command issued #1 VER CAU version 28 4 write-only 0001 Initial CAU version #0001 0010 Second version, added support for SHA-256 algorithm.(This is the value on this device) #0010 CMP0 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP 0x0 0x0 0x6 registers n CMP0 48 CR0 CMP Control Register 0 0x0 8 read-write n 0x0 0x0 FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. #000 001 One sample must agree. The comparator output is simply sampled. #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 HYSTCTR Comparator hard block hysteresis control 0 2 read-write 00 Level 0 #00 01 Level 1 #01 10 Level 2 #10 11 Level 3 #11 CR1 CMP Control Register 1 0x1 8 read-write n 0x0 0x0 COS Comparator Output Select 2 1 read-write 0 Set the filtered comparator output (CMPO) to equal COUT. #0 1 Set the unfiltered comparator output (CMPO) to equal COUTA. #1 EN Comparator Module Enable 0 1 read-write 0 Analog Comparator is disabled. #0 1 Analog Comparator is enabled. #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. #0 1 CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. #1 PMODE Power Mode Select 4 1 read-write 0 Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. #0 1 High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. #1 SE Sample Enable 7 1 read-write 0 Sampling mode is not selected. #0 1 Sampling mode is selected. #1 TRIGM Trigger Mode Enable 5 1 read-write 0 Trigger mode is disabled. #0 1 Trigger mode is enabled. #1 WE Windowing Enable 6 1 read-write 0 Windowing mode is not selected. #0 1 Windowing mode is selected. #1 DACCR DAC Control Register 0x4 8 read-write n 0x0 0x0 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference. #0 1 Vin2 is selected as resistor ladder network supply reference. #1 FPR CMP Filter Period Register 0x2 8 read-write n 0x0 0x0 FILT_PER Filter Sample Period 0 8 read-write MUXCR MUX Control Register 0x5 8 read-write n 0x0 0x0 MSEL Minus Input Mux Control 0 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSEL Plus Input Mux Control 3 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSTM Pass Through Mode Enable 7 1 read-write 0 Pass Through Mode is disabled. #0 1 Pass Through Mode is enabled. #1 SCR CMP Status and Control Register 0x3 8 read-write n 0x0 0x0 CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling-edge on COUT has not been detected. #0 1 Falling-edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising-edge on COUT has not been detected. #0 1 Rising-edge on COUT has occurred. #1 COUT Analog Comparator Output 0 1 read-only DMAEN DMA Enable Control 6 1 read-write 0 DMA is disabled. #0 1 DMA is enabled. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 CMP1 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP 0x0 0x0 0x6 registers n CMP1 49 CR0 CMP Control Register 0 0x0 8 read-write n 0x0 0x0 FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. #000 001 One sample must agree. The comparator output is simply sampled. #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 HYSTCTR Comparator hard block hysteresis control 0 2 read-write 00 Level 0 #00 01 Level 1 #01 10 Level 2 #10 11 Level 3 #11 CR1 CMP Control Register 1 0x1 8 read-write n 0x0 0x0 COS Comparator Output Select 2 1 read-write 0 Set the filtered comparator output (CMPO) to equal COUT. #0 1 Set the unfiltered comparator output (CMPO) to equal COUTA. #1 EN Comparator Module Enable 0 1 read-write 0 Analog Comparator is disabled. #0 1 Analog Comparator is enabled. #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. #0 1 CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. #1 PMODE Power Mode Select 4 1 read-write 0 Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. #0 1 High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. #1 SE Sample Enable 7 1 read-write 0 Sampling mode is not selected. #0 1 Sampling mode is selected. #1 TRIGM Trigger Mode Enable 5 1 read-write 0 Trigger mode is disabled. #0 1 Trigger mode is enabled. #1 WE Windowing Enable 6 1 read-write 0 Windowing mode is not selected. #0 1 Windowing mode is selected. #1 DACCR DAC Control Register 0x4 8 read-write n 0x0 0x0 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference. #0 1 Vin2 is selected as resistor ladder network supply reference. #1 FPR CMP Filter Period Register 0x2 8 read-write n 0x0 0x0 FILT_PER Filter Sample Period 0 8 read-write MUXCR MUX Control Register 0x5 8 read-write n 0x0 0x0 MSEL Minus Input Mux Control 0 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSEL Plus Input Mux Control 3 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSTM Pass Through Mode Enable 7 1 read-write 0 Pass Through Mode is disabled. #0 1 Pass Through Mode is enabled. #1 SCR CMP Status and Control Register 0x3 8 read-write n 0x0 0x0 CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling-edge on COUT has not been detected. #0 1 Falling-edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising-edge on COUT has not been detected. #0 1 Rising-edge on COUT has occurred. #1 COUT Analog Comparator Output 0 1 read-only DMAEN DMA Enable Control 6 1 read-write 0 DMA is disabled. #0 1 DMA is enabled. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 CRC Cyclic Redundancy Check CRC 0x0 0x0 0xC registers n CTRL CRC Control register 0x8 32 read-write n 0x0 0x0 FXOR Complement Read Of CRC Data Register 26 1 read-write 0 No XOR on reading. #0 1 Invert or complement the read value of the CRC Data register. #1 TCRC Width of CRC protocol. 24 1 read-write 0 16-bit CRC protocol. #0 1 32-bit CRC protocol. #1 TOT Type Of Transpose For Writes 30 2 read-write 00 No transposition. #00 01 Bits in bytes are transposed; bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 TOTR Type Of Transpose For Read 28 2 read-write 00 No transposition. #00 01 Bits in bytes are transposed; bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 WAS Write CRC Data Register As Seed 25 1 read-write 0 Writes to the CRC data register are data values. #0 1 Writes to the CRC data register are seed values. #1 CTRLHU CRC_CTRLHU register. 0xB 8 read-write n 0x0 0x0 FXOR no description available 2 1 read-write 0 No XOR on reading. #0 1 Invert or complement the read value of CRC data register. #1 TCRC no description available 0 1 read-write 0 16-bit CRC protocol. #0 1 32-bit CRC protocol. #1 TOT no description available 6 2 read-write 00 No Transposition. #00 01 Bits in bytes are transposed, bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 TOTR no description available 4 2 read-write 00 No Transposition. #00 01 Bits in bytes are transposed, bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 WAS no description available 1 1 read-write 0 Writes to CRC data register are data values. #0 1 Writes to CRC data reguster are seed values. #1 DATA CRC Data register CRC 0x0 32 read-write n 0x0 0x0 HL CRC High Lower Byte 16 8 read-write HU CRC High Upper Byte 24 8 read-write LL CRC Low Lower Byte 0 8 read-write LU CRC Low Upper Byte 8 8 read-write DATAH CRC_DATAH register. CRC 0x2 16 read-write n 0x0 0x0 DATAH DATAH stores the high 16 bits of the 16/32 bit CRC 0 16 read-write DATAHL CRC_DATAHL register. CRC 0x2 8 read-write n 0x0 0x0 DATAHL DATAHL stores the third 8 bits of the 32 bit CRC 0 8 read-write DATAHU CRC_DATAHU register. 0x3 8 read-write n 0x0 0x0 DATAHU DATAHU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write DATAL CRC_DATAL register. CRC 0x0 16 read-write n 0x0 0x0 DATAL DATAL stores the lower 16 bits of the 16/32 bit CRC 0 16 read-write DATALL CRC_DATALL register. CRC 0x0 8 read-write n 0x0 0x0 DATALL CRCLL stores the first 8 bits of the 32 bit DATA 0 8 read-write DATALU CRC_DATALU register. 0x1 8 read-write n 0x0 0x0 DATALU DATALL stores the second 8 bits of the 32 bit CRC 0 8 read-write GPOLY CRC Polynomial register CRC 0x4 32 read-write n 0x0 0x0 HIGH High Polynominal Half-word 16 16 read-write LOW Low Polynominal Half-word 0 16 read-write GPOLYH CRC_GPOLYH register. CRC 0x6 16 read-write n 0x0 0x0 GPOLYH POLYH stores the high 16 bits of the 16/32 bit CRC polynomial value 0 16 read-write GPOLYHL CRC_GPOLYHL register. CRC 0x6 8 read-write n 0x0 0x0 GPOLYHL POLYHL stores the third 8 bits of the 32 bit CRC 0 8 read-write GPOLYHU CRC_GPOLYHU register. 0x7 8 read-write n 0x0 0x0 GPOLYHU POLYHU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write GPOLYL CRC_GPOLYL register. CRC 0x4 16 read-write n 0x0 0x0 GPOLYL POLYL stores the lower 16 bits of the 16/32 bit CRC polynomial value 0 16 read-write GPOLYLL CRC_GPOLYLL register. CRC 0x4 8 read-write n 0x0 0x0 GPOLYLL POLYLL stores the first 8 bits of the 32 bit CRC 0 8 read-write GPOLYLU CRC_GPOLYLU register. 0x5 8 read-write n 0x0 0x0 GPOLYLU POLYLL stores the second 8 bits of the 32 bit CRC 0 8 read-write DAC0 12-Bit Digital-to-Analog Converter DAC0 0x0 0x0 0x24 registers n DAC0 45 C0 DAC Control Register 0x21 8 read-write n 0x0 0x0 DACBBIEN DAC Buffer Read Pointer Bottom Flag Interrupt Enable 0 1 read-write 0 The DAC buffer read pointer bottom flag interrupt is disabled. #0 1 The DAC buffer read pointer bottom flag interrupt is enabled. #1 DACBTIEN DAC Buffer Read Pointer Top Flag Interrupt Enable 1 1 read-write 0 The DAC buffer read pointer top flag interrupt is disabled. #0 1 The DAC buffer read pointer top flag interrupt is enabled. #1 DACBWIEN DAC Buffer Watermark Interrupt Enable 2 1 read-write 0 The DAC buffer watermark interrupt is disabled. #0 1 The DAC buffer watermark interrupt is enabled. #1 DACEN DAC Enable 7 1 read-write 0 The DAC system is disabled. #0 1 The DAC system is enabled. #1 DACRFS DAC Reference Select 6 1 read-write 0 The DAC selects DACREF_1 as the reference voltage. #0 1 The DAC selects DACREF_2 as the reference voltage. #1 DACSWTRG DAC Software Trigger 4 1 write-only 0 The DAC soft trigger is not valid. #0 1 The DAC soft trigger is valid. #1 DACTRGSEL DAC Trigger Select 5 1 read-write 0 The DAC hardware trigger is selected. #0 1 The DAC software trigger is selected. #1 LPEN DAC Low Power Control 3 1 read-write 0 High-Power mode #0 1 Low-Power mode #1 C1 DAC Control Register 1 0x22 8 read-write n 0x0 0x0 DACBFEN DAC Buffer Enable 0 1 read-write 0 Buffer read pointer is disabled. The converted data is always the first word of the buffer. #0 1 Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer. #1 DACBFMD DAC Buffer Work Mode Select 1 2 read-write 00 Normal mode #00 01 Swing mode #01 10 One-Time Scan mode #10 11 FIFO mode #11 DACBFWM DAC Buffer Watermark Select 3 2 read-write 00 In normal mode, 1 word . In FIFO mode, 2 or less than 2 data remaining in FIFO will set watermark status bit. #00 01 In normal mode, 2 words . In FIFO mode, Max/4 or less than Max/4 data remaining in FIFO will set watermark status bit. #01 10 In normal mode, 3 words . In FIFO mode, Max/2 or less than Max/2 data remaining in FIFO will set watermark status bit. #10 11 In normal mode, 4 words . In FIFO mode, Max-2 or less than Max-2 data remaining in FIFO will set watermark status bit. #11 DMAEN DMA Enable Select 7 1 read-write 0 DMA is disabled. #0 1 DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time. #1 C2 DAC Control Register 2 0x23 8 read-write n 0x0 0x0 DACBFRP DAC Buffer Read Pointer 4 4 read-write DACBFUP DAC Buffer Upper Limit 0 4 read-write DAT0H DAC Data High Register 0x2 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT0L DAC Data Low Register 0x0 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT10H DAC Data High Register 0x7A 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT10L DAC Data Low Register 0x6E 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT11H DAC Data High Register 0x91 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT11L DAC Data Low Register 0x84 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT12H DAC Data High Register 0xAA 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT12L DAC Data Low Register 0x9C 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT13H DAC Data High Register 0xC5 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT13L DAC Data Low Register 0xB6 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT14H DAC Data High Register 0xE2 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT14L DAC Data Low Register 0xD2 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT15H DAC Data High Register 0x101 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT15L DAC Data Low Register 0xF0 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT1H DAC Data High Register 0x5 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT1L DAC Data Low Register 0x2 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT2H DAC Data High Register 0xA 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT2L DAC Data Low Register 0x6 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT3H DAC Data High Register 0x11 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT3L DAC Data Low Register 0xC 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT4H DAC Data High Register 0x1A 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT4L DAC Data Low Register 0x14 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT5H DAC Data High Register 0x25 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT5L DAC Data Low Register 0x1E 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT6H DAC Data High Register 0x32 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT6L DAC Data Low Register 0x2A 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT7H DAC Data High Register 0x41 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT7L DAC Data Low Register 0x38 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT8H DAC Data High Register 0x52 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT8L DAC Data Low Register 0x48 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write DAT9H DAC Data High Register 0x65 8 read-write n 0x0 0x0 DATA1 DATA1 0 4 read-write DAT9L DAC Data Low Register 0x5A 8 read-write n 0x0 0x0 DATA0 DATA0 0 8 read-write SR DAC Status Register 0x20 8 read-write n 0x0 0x0 DACBFRPBF DAC Buffer Read Pointer Bottom Position Flag 0 1 read-write 0 The DAC buffer read pointer is not equal to C2[DACBFUP]. #0 1 The DAC buffer read pointer is equal to C2[DACBFUP]. #1 DACBFRPTF DAC Buffer Read Pointer Top Position Flag 1 1 read-write 0 The DAC buffer read pointer is not zero. #0 1 The DAC buffer read pointer is zero. #1 DACBFWMF DAC Buffer Watermark Flag 2 1 read-write 0 The DAC buffer read pointer has not reached the watermark level. #0 1 The DAC buffer read pointer has reached the watermark level. #1 DMA0 Enhanced direct memory access controller DMA 0x0 0x0 0x1100 registers n DMA0_04 0 DMA0_15 1 DMA0_26 2 DMA0_37 3 CTI0_DMA0_Error 4 CDNE Clear DONE Status Bit Register 0x1C 8 write-only n 0x0 0x0 CADN Clears All DONE Bits 6 1 write-only 0 Clears only the TCDn_CSR[DONE] bit specified in the CDNE field #0 1 Clears all bits in TCDn_CSR[DONE] #1 CDNE Clear DONE Bit 0 3 write-only NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CEEI Clear Enable Error Interrupt Register 0x18 8 write-only n 0x0 0x0 CAEE Clear All Enable Error Interrupts 6 1 write-only 0 Clear only the EEI bit specified in the CEEI field #0 1 Clear all bits in EEI #1 CEEI Clear Enable Error Interrupt 0 3 write-only NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CERQ Clear Enable Request Register 0x1A 8 write-only n 0x0 0x0 CAER Clear All Enable Requests 6 1 write-only 0 Clear only the ERQ bit specified in the CERQ field #0 1 Clear all bits in ERQ #1 CERQ Clear Enable Request 0 3 write-only NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CERR Clear Error Register 0x1E 8 write-only n 0x0 0x0 CAEI Clear All Error Indicators 6 1 write-only 0 Clear only the ERR bit specified in the CERR field #0 1 Clear all bits in ERR #1 CERR Clear Error Indicator 0 3 write-only NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CINT Clear Interrupt Request Register 0x1F 8 write-only n 0x0 0x0 CAIR Clear All Interrupt Requests 6 1 write-only 0 Clear only the INT bit specified in the CINT field #0 1 Clear all bits in INT #1 CINT Clear Interrupt Request 0 3 write-only NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CR Control Register 0x0 32 read-write n 0x0 0x0 ACTIVE DMA Active Status 31 1 read-only 0 eDMA is idle. #0 1 eDMA is executing a channel. #1 CLM Continuous Link Mode 6 1 read-write 0 A minor loop channel link made to itself goes through channel arbitration before being activated again. #0 1 A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. #1 CX Cancel Transfer 17 1 read-write 0 Normal operation #0 1 Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. #1 ECX Error Cancel Transfer 16 1 read-write 0 Normal operation #0 1 Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt. #1 EDBG Enable Debug 1 1 read-write 0 When in debug mode, the DMA continues to operate. #0 1 When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. #1 EMLM Enable Minor Loop Mapping 7 1 read-write 0 Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. #0 1 Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. #1 ERCA Enable Round Robin Channel Arbitration 2 1 read-write 0 Fixed priority arbitration is used for channel selection . #0 1 Round robin arbitration is used for channel selection . #1 HALT Halt DMA Operations 5 1 read-write 0 Normal operation #0 1 Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. #1 HOE Halt On Error 4 1 read-write 0 Normal operation #0 1 Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. #1 DCHPRI0 Channel n Priority Register 0x506 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 3 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 DCHPRI1 Channel n Priority Register 0x403 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 3 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 DCHPRI2 Channel n Priority Register 0x301 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 3 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 DCHPRI3 Channel n Priority Register 0x200 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 3 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 DCHPRI4 Channel n Priority Register 0x91C 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 3 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 DCHPRI5 Channel n Priority Register 0x815 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 3 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 DCHPRI6 Channel n Priority Register 0x70F 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 3 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 DCHPRI7 Channel n Priority Register 0x60A 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 3 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 EARS Enable Asynchronous Request in Stop Register 0x44 32 read-write n 0x0 0x0 EDREQ_0 Enable asynchronous DMA request in stop mode for channel 0. 0 1 read-write 0 Disable asynchronous DMA request for channel 0. #0 1 Enable asynchronous DMA request for channel 0. #1 EDREQ_1 Enable asynchronous DMA request in stop mode for channel 1. 1 1 read-write 0 Disable asynchronous DMA request for channel 1 #0 1 Enable asynchronous DMA request for channel 1. #1 EDREQ_2 Enable asynchronous DMA request in stop mode for channel 2. 2 1 read-write 0 Disable asynchronous DMA request for channel 2. #0 1 Enable asynchronous DMA request for channel 2. #1 EDREQ_3 Enable asynchronous DMA request in stop mode for channel 3. 3 1 read-write 0 Disable asynchronous DMA request for channel 3. #0 1 Enable asynchronous DMA request for channel 3. #1 EDREQ_4 Enable asynchronous DMA request in stop mode for channel 4 4 1 read-write 0 Disable asynchronous DMA request for channel 4. #0 1 Enable asynchronous DMA request for channel 4. #1 EDREQ_5 Enable asynchronous DMA request in stop mode for channel 5 5 1 read-write 0 Disable asynchronous DMA request for channel 5. #0 1 Enable asynchronous DMA request for channel 5. #1 EDREQ_6 Enable asynchronous DMA request in stop mode for channel 6 6 1 read-write 0 Disable asynchronous DMA request for channel 6. #0 1 Enable asynchronous DMA request for channel 6. #1 EDREQ_7 Enable asynchronous DMA request in stop mode for channel 7 7 1 read-write 0 Disable asynchronous DMA request for channel 7. #0 1 Enable asynchronous DMA request for channel 7. #1 EEI Enable Error Interrupt Register 0x14 32 read-write n 0x0 0x0 EEI0 Enable Error Interrupt 0 0 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI1 Enable Error Interrupt 1 1 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI2 Enable Error Interrupt 2 2 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI3 Enable Error Interrupt 3 3 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI4 Enable Error Interrupt 4 4 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI5 Enable Error Interrupt 5 5 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI6 Enable Error Interrupt 6 6 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI7 Enable Error Interrupt 7 7 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 ERQ Enable Request Register 0xC 32 read-write n 0x0 0x0 ERQ0 Enable DMA Request 0 0 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ1 Enable DMA Request 1 1 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ2 Enable DMA Request 2 2 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ3 Enable DMA Request 3 3 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ4 Enable DMA Request 4 4 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ5 Enable DMA Request 5 5 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ6 Enable DMA Request 6 6 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ7 Enable DMA Request 7 7 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERR Error Register 0x2C 32 read-write n 0x0 0x0 ERR0 Error In Channel 0 0 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR1 Error In Channel 1 1 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR2 Error In Channel 2 2 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR3 Error In Channel 3 3 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR4 Error In Channel 4 4 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR5 Error In Channel 5 5 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR6 Error In Channel 6 6 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR7 Error In Channel 7 7 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ES Error Status Register 0x4 32 read-only n 0x0 0x0 CPE Channel Priority Error 14 1 read-only 0 No channel priority error #0 1 The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique. #1 DAE Destination Address Error 5 1 read-only 0 No destination address configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. #1 DBE Destination Bus Error 0 1 read-only 0 No destination bus error #0 1 The last recorded error was a bus error on a destination write #1 DOE Destination Offset Error 4 1 read-only 0 No destination offset configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. #1 ECX Transfer Canceled 16 1 read-only 0 No canceled transfers #0 1 The last recorded entry was a canceled transfer by the error cancel transfer input #1 ERRCHN Error Channel Number or Canceled Channel Number 8 3 read-only NCE NBYTES/CITER Configuration Error 3 1 read-only 0 No NBYTES/CITER configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] #1 SAE Source Address Error 7 1 read-only 0 No source address configuration error. #0 1 The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. #1 SBE Source Bus Error 1 1 read-only 0 No source bus error #0 1 The last recorded error was a bus error on a source read #1 SGE Scatter/Gather Configuration Error 2 1 read-only 0 No scatter/gather configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. #1 SOE Source Offset Error 6 1 read-only 0 No source offset configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. #1 VLD Logical OR of all ERR status bits 31 1 read-only 0 No ERR bits are set. #0 1 At least one ERR bit is set indicating a valid error exists that has not been cleared. #1 HRS Hardware Request Status Register 0x34 32 read-only n 0x0 0x0 HRS0 Hardware Request Status Channel 0 0 1 read-only 0 A hardware service request for channel 0 is not present #0 1 A hardware service request for channel 0 is present #1 HRS1 Hardware Request Status Channel 1 1 1 read-only 0 A hardware service request for channel 1 is not present #0 1 A hardware service request for channel 1 is present #1 HRS2 Hardware Request Status Channel 2 2 1 read-only 0 A hardware service request for channel 2 is not present #0 1 A hardware service request for channel 2 is present #1 HRS3 Hardware Request Status Channel 3 3 1 read-only 0 A hardware service request for channel 3 is not present #0 1 A hardware service request for channel 3 is present #1 HRS4 Hardware Request Status Channel 4 4 1 read-only 0 A hardware service request for channel 4 is not present #0 1 A hardware service request for channel 4 is present #1 HRS5 Hardware Request Status Channel 5 5 1 read-only 0 A hardware service request for channel 5 is not present #0 1 A hardware service request for channel 5 is present #1 HRS6 Hardware Request Status Channel 6 6 1 read-only 0 A hardware service request for channel 6 is not present #0 1 A hardware service request for channel 6 is present #1 HRS7 Hardware Request Status Channel 7 7 1 read-only 0 A hardware service request for channel 7 is not present #0 1 A hardware service request for channel 7 is present #1 INT Interrupt Request Register 0x24 32 read-write n 0x0 0x0 INT0 Interrupt Request 0 0 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT1 Interrupt Request 1 1 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT2 Interrupt Request 2 2 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT3 Interrupt Request 3 3 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT4 Interrupt Request 4 4 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT5 Interrupt Request 5 5 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT6 Interrupt Request 6 6 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT7 Interrupt Request 7 7 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 SEEI Set Enable Error Interrupt Register 0x19 8 write-only n 0x0 0x0 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SAEE Sets All Enable Error Interrupts 6 1 write-only 0 Set only the EEI bit specified in the SEEI field. #0 1 Sets all bits in EEI #1 SEEI Set Enable Error Interrupt 0 3 write-only SERQ Set Enable Request Register 0x1B 8 write-only n 0x0 0x0 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SAER Set All Enable Requests 6 1 write-only 0 Set only the ERQ bit specified in the SERQ field #0 1 Set all bits in ERQ #1 SERQ Set Enable Request 0 3 write-only SSRT Set START Bit Register 0x1D 8 write-only n 0x0 0x0 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SAST Set All START Bits (activates all channels) 6 1 write-only 0 Set only the TCDn_CSR[START] bit specified in the SSRT field #0 1 Set all bits in TCDn_CSR[START] #1 SSRT Set START Bit 0 3 write-only TCD0_ATTR TCD Transfer Attributes 0x200C 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 101 32-byte #101 TCD0_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA0 0x203C 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD0_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA0 0x203C 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 3 read-write TCD0_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA0 0x202C 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD0_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA0 0x202C 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 3 read-write TCD0_CSR TCD Control and Status 0x2038 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 3 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD0_DADDR TCD Destination Address 0x2020 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD0_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x2030 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD0_DOFF TCD Signed Destination Address Offset 0x2028 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD0_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA0 0x2010 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD0_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA0 0x2010 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD0_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA0 0x2010 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD0_SADDR TCD Source Address 0x2000 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD0_SLAST TCD Last Source Address Adjustment 0x2018 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD0_SOFF TCD Signed Source Address Offset 0x2008 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD1_ATTR TCD Transfer Attributes 0x3032 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 101 32-byte #101 TCD1_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA0 0x307A 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD1_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA0 0x307A 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 3 read-write TCD1_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA0 0x3062 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD1_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA0 0x3062 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 3 read-write TCD1_CSR TCD Control and Status 0x3074 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 3 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD1_DADDR TCD Destination Address 0x3050 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD1_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x3068 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD1_DOFF TCD Signed Destination Address Offset 0x305C 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD1_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA0 0x3038 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD1_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA0 0x3038 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD1_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA0 0x3038 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD1_SADDR TCD Source Address 0x3020 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD1_SLAST TCD Last Source Address Adjustment 0x3044 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD1_SOFF TCD Signed Source Address Offset 0x302C 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD2_ATTR TCD Transfer Attributes 0x4078 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 101 32-byte #101 TCD2_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA0 0x40D8 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD2_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA0 0x40D8 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 3 read-write TCD2_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA0 0x40B8 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD2_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA0 0x40B8 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 3 read-write TCD2_CSR TCD Control and Status 0x40D0 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 3 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD2_DADDR TCD Destination Address 0x40A0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD2_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x40C0 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD2_DOFF TCD Signed Destination Address Offset 0x40B0 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD2_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA0 0x4080 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD2_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA0 0x4080 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD2_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA0 0x4080 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD2_SADDR TCD Source Address 0x4060 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD2_SLAST TCD Last Source Address Adjustment 0x4090 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD2_SOFF TCD Signed Source Address Offset 0x4070 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD3_ATTR TCD Transfer Attributes 0x50DE 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 101 32-byte #101 TCD3_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA0 0x5156 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD3_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA0 0x5156 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 3 read-write TCD3_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA0 0x512E 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD3_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA0 0x512E 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 3 read-write TCD3_CSR TCD Control and Status 0x514C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 3 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD3_DADDR TCD Destination Address 0x5110 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD3_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x5138 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD3_DOFF TCD Signed Destination Address Offset 0x5124 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD3_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA0 0x50E8 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD3_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA0 0x50E8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD3_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA0 0x50E8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD3_SADDR TCD Source Address 0x50C0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD3_SLAST TCD Last Source Address Adjustment 0x50FC 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD3_SOFF TCD Signed Source Address Offset 0x50D4 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD4_ATTR TCD Transfer Attributes 0x6164 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 101 32-byte #101 TCD4_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA0 0x61F4 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD4_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA0 0x61F4 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 3 read-write TCD4_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA0 0x61C4 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD4_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA0 0x61C4 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 3 read-write TCD4_CSR TCD Control and Status 0x61E8 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 3 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD4_DADDR TCD Destination Address 0x61A0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD4_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x61D0 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD4_DOFF TCD Signed Destination Address Offset 0x61B8 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD4_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA0 0x6170 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD4_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA0 0x6170 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD4_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA0 0x6170 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD4_SADDR TCD Source Address 0x6140 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD4_SLAST TCD Last Source Address Adjustment 0x6188 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD4_SOFF TCD Signed Source Address Offset 0x6158 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD5_ATTR TCD Transfer Attributes 0x720A 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 101 32-byte #101 TCD5_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA0 0x72B2 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD5_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA0 0x72B2 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 3 read-write TCD5_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA0 0x727A 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD5_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA0 0x727A 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 3 read-write TCD5_CSR TCD Control and Status 0x72A4 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 3 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD5_DADDR TCD Destination Address 0x7250 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD5_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x7288 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD5_DOFF TCD Signed Destination Address Offset 0x726C 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD5_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA0 0x7218 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD5_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA0 0x7218 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD5_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA0 0x7218 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD5_SADDR TCD Source Address 0x71E0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD5_SLAST TCD Last Source Address Adjustment 0x7234 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD5_SOFF TCD Signed Source Address Offset 0x71FC 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD6_ATTR TCD Transfer Attributes 0x82D0 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 101 32-byte #101 TCD6_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA0 0x8390 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD6_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA0 0x8390 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 3 read-write TCD6_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA0 0x8350 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD6_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA0 0x8350 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 3 read-write TCD6_CSR TCD Control and Status 0x8380 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 3 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD6_DADDR TCD Destination Address 0x8320 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD6_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x8360 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD6_DOFF TCD Signed Destination Address Offset 0x8340 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD6_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA0 0x82E0 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD6_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA0 0x82E0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD6_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA0 0x82E0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD6_SADDR TCD Source Address 0x82A0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD6_SLAST TCD Last Source Address Adjustment 0x8300 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD6_SOFF TCD Signed Source Address Offset 0x82C0 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD7_ATTR TCD Transfer Attributes 0x93B6 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 101 32-byte #101 TCD7_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA0 0x948E 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD7_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA0 0x948E 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 3 read-write TCD7_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA0 0x9446 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD7_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA0 0x9446 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 3 read-write TCD7_CSR TCD Control and Status 0x947C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 3 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD7_DADDR TCD Destination Address 0x9410 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD7_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x9458 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD7_DOFF TCD Signed Destination Address Offset 0x9434 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD7_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA0 0x93C8 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD7_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA0 0x93C8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD7_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA0 0x93C8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD7_SADDR TCD Source Address 0x9380 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD7_SLAST TCD Last Source Address Adjustment 0x93EC 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD7_SOFF TCD Signed Source Address Offset 0x93A4 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write DMA1 Enhanced direct memory access controller DMA 0x0 0x0 0x1100 registers n DMA1_04 56 DMA1_15 57 DMA1_26 58 DMA1_37 59 DMA1_Error 60 CDNE Clear DONE Status Bit Register 0x1C 8 write-only n 0x0 0x0 CADN Clears All DONE Bits 6 1 write-only 0 Clears only the TCDn_CSR[DONE] bit specified in the CDNE field #0 1 Clears all bits in TCDn_CSR[DONE] #1 CDNE Clear DONE Bit 0 3 write-only NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CEEI Clear Enable Error Interrupt Register 0x18 8 write-only n 0x0 0x0 CAEE Clear All Enable Error Interrupts 6 1 write-only 0 Clear only the EEI bit specified in the CEEI field #0 1 Clear all bits in EEI #1 CEEI Clear Enable Error Interrupt 0 3 write-only NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CERQ Clear Enable Request Register 0x1A 8 write-only n 0x0 0x0 CAER Clear All Enable Requests 6 1 write-only 0 Clear only the ERQ bit specified in the CERQ field #0 1 Clear all bits in ERQ #1 CERQ Clear Enable Request 0 3 write-only NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CERR Clear Error Register 0x1E 8 write-only n 0x0 0x0 CAEI Clear All Error Indicators 6 1 write-only 0 Clear only the ERR bit specified in the CERR field #0 1 Clear all bits in ERR #1 CERR Clear Error Indicator 0 3 write-only NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CINT Clear Interrupt Request Register 0x1F 8 write-only n 0x0 0x0 CAIR Clear All Interrupt Requests 6 1 write-only 0 Clear only the INT bit specified in the CINT field #0 1 Clear all bits in INT #1 CINT Clear Interrupt Request 0 3 write-only NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 CR Control Register 0x0 32 read-write n 0x0 0x0 ACTIVE DMA Active Status 31 1 read-only 0 eDMA is idle. #0 1 eDMA is executing a channel. #1 CLM Continuous Link Mode 6 1 read-write 0 A minor loop channel link made to itself goes through channel arbitration before being activated again. #0 1 A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. #1 CX Cancel Transfer 17 1 read-write 0 Normal operation #0 1 Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. #1 ECX Error Cancel Transfer 16 1 read-write 0 Normal operation #0 1 Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt. #1 EDBG Enable Debug 1 1 read-write 0 When in debug mode, the DMA continues to operate. #0 1 When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. #1 EMLM Enable Minor Loop Mapping 7 1 read-write 0 Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. #0 1 Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. #1 ERCA Enable Round Robin Channel Arbitration 2 1 read-write 0 Fixed priority arbitration is used for channel selection . #0 1 Round robin arbitration is used for channel selection . #1 HALT Halt DMA Operations 5 1 read-write 0 Normal operation #0 1 Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. #1 HOE Halt On Error 4 1 read-write 0 Normal operation #0 1 Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. #1 DCHPRI0 Channel n Priority Register 0x506 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 3 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 DCHPRI1 Channel n Priority Register 0x403 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 3 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 DCHPRI2 Channel n Priority Register 0x301 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 3 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 DCHPRI3 Channel n Priority Register 0x200 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 3 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 DCHPRI4 Channel n Priority Register 0x91C 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 3 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 DCHPRI5 Channel n Priority Register 0x815 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 3 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 DCHPRI6 Channel n Priority Register 0x70F 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 3 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 DCHPRI7 Channel n Priority Register 0x60A 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 3 read-write DPA Disable Preempt Ability. 6 1 read-write 0 Channel n can suspend a lower priority channel. #0 1 Channel n cannot suspend any channel, regardless of channel priority. #1 ECP Enable Channel Preemption. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request. #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel. #1 EARS Enable Asynchronous Request in Stop Register 0x44 32 read-write n 0x0 0x0 EDREQ_0 Enable asynchronous DMA request in stop mode for channel 0. 0 1 read-write 0 Disable asynchronous DMA request for channel 0. #0 1 Enable asynchronous DMA request for channel 0. #1 EDREQ_1 Enable asynchronous DMA request in stop mode for channel 1. 1 1 read-write 0 Disable asynchronous DMA request for channel 1 #0 1 Enable asynchronous DMA request for channel 1. #1 EDREQ_2 Enable asynchronous DMA request in stop mode for channel 2. 2 1 read-write 0 Disable asynchronous DMA request for channel 2. #0 1 Enable asynchronous DMA request for channel 2. #1 EDREQ_3 Enable asynchronous DMA request in stop mode for channel 3. 3 1 read-write 0 Disable asynchronous DMA request for channel 3. #0 1 Enable asynchronous DMA request for channel 3. #1 EDREQ_4 Enable asynchronous DMA request in stop mode for channel 4 4 1 read-write 0 Disable asynchronous DMA request for channel 4. #0 1 Enable asynchronous DMA request for channel 4. #1 EDREQ_5 Enable asynchronous DMA request in stop mode for channel 5 5 1 read-write 0 Disable asynchronous DMA request for channel 5. #0 1 Enable asynchronous DMA request for channel 5. #1 EDREQ_6 Enable asynchronous DMA request in stop mode for channel 6 6 1 read-write 0 Disable asynchronous DMA request for channel 6. #0 1 Enable asynchronous DMA request for channel 6. #1 EDREQ_7 Enable asynchronous DMA request in stop mode for channel 7 7 1 read-write 0 Disable asynchronous DMA request for channel 7. #0 1 Enable asynchronous DMA request for channel 7. #1 EEI Enable Error Interrupt Register 0x14 32 read-write n 0x0 0x0 EEI0 Enable Error Interrupt 0 0 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI1 Enable Error Interrupt 1 1 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI2 Enable Error Interrupt 2 2 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI3 Enable Error Interrupt 3 3 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI4 Enable Error Interrupt 4 4 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI5 Enable Error Interrupt 5 5 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI6 Enable Error Interrupt 6 6 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI7 Enable Error Interrupt 7 7 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 ERQ Enable Request Register 0xC 32 read-write n 0x0 0x0 ERQ0 Enable DMA Request 0 0 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ1 Enable DMA Request 1 1 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ2 Enable DMA Request 2 2 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ3 Enable DMA Request 3 3 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ4 Enable DMA Request 4 4 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ5 Enable DMA Request 5 5 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ6 Enable DMA Request 6 6 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ7 Enable DMA Request 7 7 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERR Error Register 0x2C 32 read-write n 0x0 0x0 ERR0 Error In Channel 0 0 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR1 Error In Channel 1 1 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR2 Error In Channel 2 2 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR3 Error In Channel 3 3 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR4 Error In Channel 4 4 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR5 Error In Channel 5 5 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR6 Error In Channel 6 6 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ERR7 Error In Channel 7 7 1 read-write 0 An error in this channel has not occurred #0 1 An error in this channel has occurred #1 ES Error Status Register 0x4 32 read-only n 0x0 0x0 CPE Channel Priority Error 14 1 read-only 0 No channel priority error #0 1 The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique. #1 DAE Destination Address Error 5 1 read-only 0 No destination address configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. #1 DBE Destination Bus Error 0 1 read-only 0 No destination bus error #0 1 The last recorded error was a bus error on a destination write #1 DOE Destination Offset Error 4 1 read-only 0 No destination offset configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. #1 ECX Transfer Canceled 16 1 read-only 0 No canceled transfers #0 1 The last recorded entry was a canceled transfer by the error cancel transfer input #1 ERRCHN Error Channel Number or Canceled Channel Number 8 3 read-only NCE NBYTES/CITER Configuration Error 3 1 read-only 0 No NBYTES/CITER configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] #1 SAE Source Address Error 7 1 read-only 0 No source address configuration error. #0 1 The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. #1 SBE Source Bus Error 1 1 read-only 0 No source bus error #0 1 The last recorded error was a bus error on a source read #1 SGE Scatter/Gather Configuration Error 2 1 read-only 0 No scatter/gather configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. #1 SOE Source Offset Error 6 1 read-only 0 No source offset configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. #1 VLD Logical OR of all ERR status bits 31 1 read-only 0 No ERR bits are set. #0 1 At least one ERR bit is set indicating a valid error exists that has not been cleared. #1 HRS Hardware Request Status Register 0x34 32 read-only n 0x0 0x0 HRS0 Hardware Request Status Channel 0 0 1 read-only 0 A hardware service request for channel 0 is not present #0 1 A hardware service request for channel 0 is present #1 HRS1 Hardware Request Status Channel 1 1 1 read-only 0 A hardware service request for channel 1 is not present #0 1 A hardware service request for channel 1 is present #1 HRS2 Hardware Request Status Channel 2 2 1 read-only 0 A hardware service request for channel 2 is not present #0 1 A hardware service request for channel 2 is present #1 HRS3 Hardware Request Status Channel 3 3 1 read-only 0 A hardware service request for channel 3 is not present #0 1 A hardware service request for channel 3 is present #1 HRS4 Hardware Request Status Channel 4 4 1 read-only 0 A hardware service request for channel 4 is not present #0 1 A hardware service request for channel 4 is present #1 HRS5 Hardware Request Status Channel 5 5 1 read-only 0 A hardware service request for channel 5 is not present #0 1 A hardware service request for channel 5 is present #1 HRS6 Hardware Request Status Channel 6 6 1 read-only 0 A hardware service request for channel 6 is not present #0 1 A hardware service request for channel 6 is present #1 HRS7 Hardware Request Status Channel 7 7 1 read-only 0 A hardware service request for channel 7 is not present #0 1 A hardware service request for channel 7 is present #1 INT Interrupt Request Register 0x24 32 read-write n 0x0 0x0 INT0 Interrupt Request 0 0 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT1 Interrupt Request 1 1 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT2 Interrupt Request 2 2 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT3 Interrupt Request 3 3 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT4 Interrupt Request 4 4 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT5 Interrupt Request 5 5 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT6 Interrupt Request 6 6 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT7 Interrupt Request 7 7 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 SEEI Set Enable Error Interrupt Register 0x19 8 write-only n 0x0 0x0 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SAEE Sets All Enable Error Interrupts 6 1 write-only 0 Set only the EEI bit specified in the SEEI field. #0 1 Sets all bits in EEI #1 SEEI Set Enable Error Interrupt 0 3 write-only SERQ Set Enable Request Register 0x1B 8 write-only n 0x0 0x0 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SAER Set All Enable Requests 6 1 write-only 0 Set only the ERQ bit specified in the SERQ field #0 1 Set all bits in ERQ #1 SERQ Set Enable Request 0 3 write-only SSRT Set START Bit Register 0x1D 8 write-only n 0x0 0x0 NOP No Op enable 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 SAST Set All START Bits (activates all channels) 6 1 write-only 0 Set only the TCDn_CSR[START] bit specified in the SSRT field #0 1 Set all bits in TCDn_CSR[START] #1 SSRT Set START Bit 0 3 write-only TCD0_ATTR TCD Transfer Attributes 0x200C 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 101 32-byte #101 TCD0_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA1 0x203C 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD0_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA1 0x203C 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 3 read-write TCD0_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA1 0x202C 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD0_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA1 0x202C 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 3 read-write TCD0_CSR TCD Control and Status 0x2038 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 3 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD0_DADDR TCD Destination Address 0x2020 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD0_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x2030 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD0_DOFF TCD Signed Destination Address Offset 0x2028 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD0_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA1 0x2010 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD0_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA1 0x2010 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD0_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA1 0x2010 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD0_SADDR TCD Source Address 0x2000 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD0_SLAST TCD Last Source Address Adjustment 0x2018 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD0_SOFF TCD Signed Source Address Offset 0x2008 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD1_ATTR TCD Transfer Attributes 0x3032 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 101 32-byte #101 TCD1_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA1 0x307A 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD1_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA1 0x307A 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 3 read-write TCD1_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA1 0x3062 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD1_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA1 0x3062 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 3 read-write TCD1_CSR TCD Control and Status 0x3074 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 3 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD1_DADDR TCD Destination Address 0x3050 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD1_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x3068 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD1_DOFF TCD Signed Destination Address Offset 0x305C 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD1_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA1 0x3038 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD1_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA1 0x3038 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD1_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA1 0x3038 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD1_SADDR TCD Source Address 0x3020 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD1_SLAST TCD Last Source Address Adjustment 0x3044 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD1_SOFF TCD Signed Source Address Offset 0x302C 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD2_ATTR TCD Transfer Attributes 0x4078 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 101 32-byte #101 TCD2_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA1 0x40D8 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD2_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA1 0x40D8 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 3 read-write TCD2_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA1 0x40B8 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD2_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA1 0x40B8 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 3 read-write TCD2_CSR TCD Control and Status 0x40D0 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 3 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD2_DADDR TCD Destination Address 0x40A0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD2_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x40C0 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD2_DOFF TCD Signed Destination Address Offset 0x40B0 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD2_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA1 0x4080 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD2_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA1 0x4080 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD2_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA1 0x4080 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD2_SADDR TCD Source Address 0x4060 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD2_SLAST TCD Last Source Address Adjustment 0x4090 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD2_SOFF TCD Signed Source Address Offset 0x4070 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD3_ATTR TCD Transfer Attributes 0x50DE 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 101 32-byte #101 TCD3_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA1 0x5156 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD3_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA1 0x5156 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 3 read-write TCD3_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA1 0x512E 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD3_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA1 0x512E 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 3 read-write TCD3_CSR TCD Control and Status 0x514C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 3 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD3_DADDR TCD Destination Address 0x5110 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD3_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x5138 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD3_DOFF TCD Signed Destination Address Offset 0x5124 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD3_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA1 0x50E8 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD3_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA1 0x50E8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD3_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA1 0x50E8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD3_SADDR TCD Source Address 0x50C0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD3_SLAST TCD Last Source Address Adjustment 0x50FC 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD3_SOFF TCD Signed Source Address Offset 0x50D4 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD4_ATTR TCD Transfer Attributes 0x6164 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 101 32-byte #101 TCD4_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA1 0x61F4 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD4_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA1 0x61F4 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 3 read-write TCD4_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA1 0x61C4 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD4_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA1 0x61C4 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 3 read-write TCD4_CSR TCD Control and Status 0x61E8 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 3 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD4_DADDR TCD Destination Address 0x61A0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD4_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x61D0 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD4_DOFF TCD Signed Destination Address Offset 0x61B8 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD4_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA1 0x6170 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD4_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA1 0x6170 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD4_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA1 0x6170 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD4_SADDR TCD Source Address 0x6140 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD4_SLAST TCD Last Source Address Adjustment 0x6188 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD4_SOFF TCD Signed Source Address Offset 0x6158 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD5_ATTR TCD Transfer Attributes 0x720A 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 101 32-byte #101 TCD5_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA1 0x72B2 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD5_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA1 0x72B2 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 3 read-write TCD5_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA1 0x727A 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD5_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA1 0x727A 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 3 read-write TCD5_CSR TCD Control and Status 0x72A4 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 3 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD5_DADDR TCD Destination Address 0x7250 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD5_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x7288 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD5_DOFF TCD Signed Destination Address Offset 0x726C 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD5_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA1 0x7218 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD5_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA1 0x7218 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD5_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA1 0x7218 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD5_SADDR TCD Source Address 0x71E0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD5_SLAST TCD Last Source Address Adjustment 0x7234 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD5_SOFF TCD Signed Source Address Offset 0x71FC 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD6_ATTR TCD Transfer Attributes 0x82D0 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 101 32-byte #101 TCD6_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA1 0x8390 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD6_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA1 0x8390 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 3 read-write TCD6_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA1 0x8350 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD6_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA1 0x8350 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 3 read-write TCD6_CSR TCD Control and Status 0x8380 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 3 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD6_DADDR TCD Destination Address 0x8320 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD6_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x8360 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD6_DOFF TCD Signed Destination Address Offset 0x8340 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD6_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA1 0x82E0 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD6_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA1 0x82E0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD6_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA1 0x82E0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD6_SADDR TCD Source Address 0x82A0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD6_SLAST TCD Last Source Address Adjustment 0x8300 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD6_SOFF TCD Signed Source Address Offset 0x82C0 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD7_ATTR TCD Transfer Attributes 0x93B6 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #00000 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 100 16-byte #100 101 32-byte #101 TCD7_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA1 0x948E 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD7_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA1 0x948E 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 3 read-write TCD7_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA1 0x9446 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD7_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA1 0x9446 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Minor Loop Link Channel Number 9 3 read-write TCD7_CSR TCD Control and Status 0x947C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls. #00 10 eDMA engine stalls for 4 cycles after each R/W. #10 11 eDMA engine stalls for 8 cycles after each R/W. #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected. #0 1 The channel's ERQ bit is cleared when the major loop is complete. #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled. #0 1 The half-point interrupt is enabled. #1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write 0 The end-of-major loop interrupt is disabled. #0 1 The end-of-major loop interrupt is enabled. #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled. #0 1 The channel-to-channel linking is enabled. #1 MAJORLINKCH Major Loop Link Channel Number 8 3 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started. #0 1 The channel is explicitly started via a software initiated service request. #1 TCD7_DADDR TCD Destination Address 0x9410 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD7_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x9458 32 read-write n 0x0 0x0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) 0 32 read-write TCD7_DOFF TCD Signed Destination Address Offset 0x9434 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD7_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) DMA1 0x93C8 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD7_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) DMA1 0x93C8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD7_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) DMA1 0x93C8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD7_SADDR TCD Source Address 0x9380 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD7_SLAST TCD Last Source Address Adjustment 0x93EC 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD7_SOFF TCD Signed Source Address Offset 0x93A4 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write DMAMUX0 DMA channel multiplexor DMAMUX 0x0 0x0 0x8 registers n CHCFG0 Channel Configuration register 0x0 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG1 Channel Configuration register 0x1 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG2 Channel Configuration register 0x3 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG3 Channel Configuration register 0x6 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG4 Channel Configuration register 0xA 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG5 Channel Configuration register 0xF 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG6 Channel Configuration register 0x15 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG7 Channel Configuration register 0x1C 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 DMAMUX1 DMA channel multiplexor DMAMUX 0x0 0x0 0x8 registers n CHCFG0 Channel Configuration register 0x0 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG1 Channel Configuration register 0x1 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG2 Channel Configuration register 0x3 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG3 Channel Configuration register 0x6 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG4 Channel Configuration register 0xA 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG5 Channel Configuration register 0xF 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG6 Channel Configuration register 0x15 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 CHCFG7 Channel Configuration register 0x1C 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (Slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) #0 1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. #1 EMVSIM0 EMVSIM EMVSIM0 0x0 0x0 0x4C registers n EMVSIM0 38 BGT_VAL Block Guard Time Value Register 0x40 32 read-write n 0x0 0x0 BGT Block Guard Time Value 0 16 read-write BWT_VAL Block Wait Time Value Register 0x3C 32 read-write n 0x0 0x0 BWT Block Wait Time Value 0 32 read-write CLKCFG Clock Configuration Register 0x8 32 read-write n 0x0 0x0 CLK_PRSC Clock Prescaler Value 0 8 read-write 10 Divide by 2 #10 GPCNT0_CLK_SEL General Purpose Counter 0 Clock Select 10 2 read-write 00 Disabled / Reset (default) #00 01 Card Clock #01 10 Receive Clock #10 11 ETU Clock (transmit clock) #11 GPCNT1_CLK_SEL General Purpose Counter 1 Clock Select 8 2 read-write 00 Disabled / Reset (default) #00 01 Card Clock #01 10 Receive Clock #10 11 ETU Clock (transmit clock) #11 CTRL Control Register 0x10 32 read-write n 0x0 0x0 ANACK Auto NACK Enable 2 1 read-write 0 NACK generation on errors disabled #0 1 NACK generation on errors enabled (default) #1 BWT_EN Block Wait Time Counter Enable 31 1 read-write 0 Disable BWT, BGT Counters (default) #0 1 Enable BWT, BGT Counters #1 CRC_EN CRC Enable 29 1 read-write 0 16-bit Cyclic Redundancy Checking disabled (default) #0 1 16-bit Cyclic Redundancy Checking enabled #1 CRC_IN_FLIP CRC Input Byte's Bit Reversal or Flip Control 26 1 read-write 0 Bits in the input byte will not be reversed (i.e. 7:0 will remain 7:0) before the CRC calculation (default) #0 1 Bits in the input byte will be reversed (i.e. 7:0 will become 0:7) before CRC calculation #1 CRC_OUT_FLIP CRC Output Value Bit Reversal or Flip 25 1 read-write 0 Bits within the CRC output bytes will not be reversed i.e. 15:0 will remain 15:0 (default) #0 1 Bits within the CRC output bytes will be reversed i.e. 15:0 will become {8:15,0:7} #1 CWT_EN Character Wait Time Counter Enable 27 1 read-write 0 Character Wait time Counter is disabled (default) #0 1 Character Wait time counter is enabled #1 DOZE_EN Doze Enable 12 1 read-write 0 DOZE instruction will gate all internal EMV SIM clocks as well as the Smart Card clock when the transmit FIFO is empty (default) #0 1 DOZE instruction has no effect on EMV SIM module #1 FLSH_RX Flush Receiver Bit 8 1 write-only 0 EMV SIM Receiver normal operation (default) #0 1 EMV SIM Receiver held in Reset #1 FLSH_TX Flush Transmitter Bit 9 1 write-only 0 EMV SIM Transmitter normal operation (default) #0 1 EMV SIM Transmitter held in Reset #1 IC Inverse Convention 0 1 read-write 0 Direction convention transfers enabled (default) #0 1 Inverse convention transfers enabled #1 ICM Initial Character Mode 1 1 read-write 0 Initial Character Mode disabled #0 1 Initial Character Mode enabled (default) #1 INV_CRC_VAL Invert bits in the CRC Output Value 24 1 read-write 0 Bits in CRC Output value will not be inverted. #0 1 Bits in CRC Output value will be inverted. (default) #1 KILL_CLOCKS Kill all internal clocks 11 1 read-write 0 EMV SIM input clock enabled (default) #0 1 EMV SIM input clock is disabled #1 LRC_EN LRC Enable 28 1 read-write 0 8-bit Linear Redundancy Checking disabled (default) #0 1 8-bit Linear Redundancy Checking enabled #1 ONACK Overrun NACK Enable 3 1 read-write 0 NACK generation on overrun is disabled (default) #0 1 NACK generation on overrun is enabled #1 RCVR_11 Receiver 11 ETU Mode Enable 18 1 read-write 0 Receiver configured for 12 ETU operation mode (default) #0 1 Receiver configured for 11 ETU operation mode #1 RCV_EN Receiver Enable 16 1 read-write 0 EMV SIM Receiver disabled (default) #0 1 EMV SIM Receiver enabled #1 RX_DMA_EN Receive DMA Enable 19 1 read-write 0 No DMA Read Request asserted for Receiver (default) #0 1 DMA Read Request asserted for Receiver #1 STOP_EN STOP Enable 13 1 read-write 0 STOP instruction shuts down all EMV SIM clocks (default) #0 1 STOP instruction shuts down all clocks except for the Smart Card Clock (SCK) (clock provided to Smart Card) #1 SW_RST Software Reset Bit 10 1 write-only 0 EMV SIM Normal operation (default) #0 1 EMV SIM held in Reset #1 TX_DMA_EN Transmit DMA Enable 20 1 read-write 0 No DMA Write Request asserted for Transmitter (default) #0 1 DMA Write Request asserted for Transmitter #1 XMT_CRC_LRC Transmit CRC or LRC Enable 30 1 read-write 0 No CRC or LRC value is transmitted (default) #0 1 Transmit LRC or CRC info when FIFO empties (whichever is enabled) #1 XMT_EN Transmitter Enable 17 1 read-write 0 EMV SIM Transmitter disabled (default) #0 1 EMV SIM Transmitter enabled #1 CWT_VAL Character Wait Time Value Register 0x38 32 read-write n 0x0 0x0 CWT Character Wait Time Value 0 16 read-write DIVISOR Baud Rate Divisor Register 0xC 32 read-write n 0x0 0x0 DIVISOR_VALUE Divisor (F/D) Value 0 9 read-write 101110100 Divisor value for F = 372 and D = 1 (default) #101110100 GPCNT0_VAL General Purpose Counter 0 Timeout Value Register 0x44 32 read-write n 0x0 0x0 GPCNT0 General Purpose Counter 0 Timeout Value 0 16 read-write GPCNT1_VAL General Purpose Counter 1 Timeout Value 0x48 32 read-write n 0x0 0x0 GPCNT1 General Purpose Counter 1 Timeout Value 0 16 read-write INT_MASK Interrupt Mask Register 0x14 32 read-write n 0x0 0x0 BGT_ERR_IM Block Guard Time Error Interrupt 12 1 read-write 0 BGT_ERR interrupt enabled #0 1 BGT_ERR interrupt masked (default) #1 BWT_ERR_IM Block Wait Time Error Interrupt Mask 11 1 read-write 0 BWT_ERR interrupt enabled #0 1 BWT_ERR interrupt masked (default) #1 CWT_ERR_IM Character Wait Time Error Interrupt Mask 9 1 read-write 0 CWT_ERR interrupt enabled #0 1 CWT_ERR interrupt masked (default) #1 ETC_IM Early Transmit Complete Interrupt Mask 3 1 read-write 0 ETC interrupt enabled #0 1 ETC interrupt masked (default) #1 GPCNT0_IM General Purpose Timer 0 Timeout Interrupt Mask 8 1 read-write 0 GPCNT0_TO interrupt enabled #0 1 GPCNT0_TO interrupt masked (default) #1 GPCNT1_IM General Purpose Counter 1 Timeout Interrupt Mask 13 1 read-write 0 GPCNT1_TO interrupt enabled #0 1 GPCNT1_TO interrupt masked (default) #1 PEF_IM Parity Error Interrupt Mask 15 1 read-write 0 PEF interrupt enabled #0 1 PEF interrupt masked (default) #1 RDT_IM Receive Data Threshold Interrupt Mask 0 1 read-write 0 RDTF interrupt enabled #0 1 RDTF interrupt masked (default) #1 RFO_IM Receive FIFO Overflow Interrupt Mask 2 1 read-write 0 RFO interrupt enabled #0 1 RFO interrupt masked (default) #1 RNACK_IM Receiver NACK Threshold Interrupt Mask 10 1 read-write 0 RTE interrupt enabled #0 1 RTE interrupt masked (default) #1 RX_DATA_IM Receive Data Interrupt Mask 14 1 read-write 0 RX_DATA interrupt enabled #0 1 RX_DATA interrupt masked (default) #1 TC_IM Transmit Complete Interrupt Mask 1 1 read-write 0 TCF interrupt enabled #0 1 TCF interrupt masked (default) #1 TDT_IM Transmit Data Threshold Interrupt Mask 7 1 read-write 0 TDTF interrupt enabled #0 1 TDTF interrupt masked (default) #1 TFE_IM Transmit FIFO Empty Interrupt Mask 4 1 read-write 0 TFE interrupt enabled #0 1 TFE interrupt masked (default) #1 TFF_IM Transmit FIFO Full Interrupt Mask 6 1 read-write 0 TFF interrupt enabled #0 1 TFF interrupt masked (default) #1 TNACK_IM Transmit NACK Threshold Interrupt Mask 5 1 read-write 0 TNTE interrupt enabled #0 1 TNTE interrupt masked (default) #1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 RX_FIFO_DEPTH Receive FIFO Depth 0 8 read-only TX_FIFO_DEPTH Transmit FIFO Depth 8 8 read-only PCSR Port Control and Status Register 0x28 32 read-write n 0x0 0x0 SAPD Auto Power Down Enable 0 1 read-write 0 Auto power down disabled (default) #0 1 Auto power down enabled #1 SCEN Clock Enable for Smart Card 4 1 read-write 0 Smart Card Clock Disabled #0 1 Smart Card Clock Enabled #1 SCSP Smart Card Clock Stop Polarity 5 1 read-write 0 Clock is logic 0 when stopped by SCEN #0 1 Clock is logic 1 when stopped by SCEN #1 SPD Auto Power Down Control 7 1 read-write 0 No effect (default) #0 1 Start Auto Powerdown or Power Down is in progress #1 SPDES SIM Presence Detect Edge Select 27 1 read-write 0 Falling edge on the pin (default) #0 1 Rising edge on the pin #1 SPDIF Smart Card Presence Detect Interrupt Flag 25 1 read-write 0 No insertion or removal of Smart Card detected on Port (default) #0 1 Insertion or removal of Smart Card detected on Port #1 SPDIM Smart Card Presence Detect Interrupt Mask 24 1 read-write 0 SIM presence detect interrupt is enabled #0 1 SIM presence detect interrupt is masked (default) #1 SPDP Smart Card Presence Detect Pin Status 26 1 read-only 0 SIM Presence Detect pin is logic low #0 1 SIM Presence Detectpin is logic high #1 SRST Reset to Smart Card 3 1 read-write 0 Smart Card Reset is asserted (default) #0 1 Smart Card Reset is de-asserted #1 SVCC_EN Vcc Enable for Smart Card 1 1 read-write 0 Smart Card Voltage disabled (default) #0 1 Smart Card Voltage enabled #1 VCCENP VCC Enable Polarity Control 2 1 read-write 0 VCC_EN is active high. Polarity of SVCC_EN is unchanged. #0 1 VCC_EN is active low. Polarity of SVCC_EN is inverted. #1 RX_BUF Receive Data Read Buffer 0x2C 32 read-only n 0x0 0x0 RX_BYTE Receive Data Byte Read 0 8 read-only RX_STATUS Receive Status Register 0x20 32 read-write n 0x0 0x0 BGT_ERR Block Guard Time Error Flag 11 1 read-write 0 Block guard time was sufficient #0 1 Block guard time was too small #1 BWT_ERR Block Wait Time Error Flag 10 1 read-write 0 Block wait time not exceeded #0 1 Block wait time was exceeded #1 CRC_OK CRC Check OK Flag 7 1 read-only 0 Current CRC value does not match remainder. #0 1 Current calculated CRC value matches the expected result. #1 CWT_ERR Character Wait Time Error Flag 8 1 read-write 0 No CWT violation has occurred (default). #0 1 Time between two consecutive characters has exceeded the value in CHAR_WAIT. #1 FEF Frame Error Flag 13 1 read-write 0 No frame error detected #0 1 Frame error detected #1 LRC_OK LRC Check OK Flag 6 1 read-only 0 Current LRC value does not match remainder. #0 1 Current calculated LRC value matches the expected result (i.e. zero). #1 PEF Parity Error Flag 12 1 read-write 0 No parity error detected #0 1 Parity error detected #1 RDTF Receive Data Threshold Interrupt Flag 5 1 read-only 0 Number of unread bytes in receive FIFO less than the value set by RDT[3:0] (default). #0 1 Number of unread bytes in receive FIFO greater or than equal to value set by RDT[3:0]. #1 RFO Receive FIFO Overflow Flag 0 1 read-write 0 No overrun error has occurred (default) #0 1 A byte was received when the received FIFO was already full #1 RTE Received NACK Threshold Error Flag 9 1 read-write 0 Number of NACKs generated by the receiver is less than the value programmed in RTH[3:0] #0 1 Number of NACKs generated by the receiver is equal to the value programmed in RTH[3:0] #1 RX_CNT Receive FIFO Byte Count 22 3 read-only 0 FIFO is emtpy #000 RX_DATA Receive Data Interrupt Flag 4 1 read-write 0 No new byte is received #0 1 New byte is received ans stored in Receive FIFO #1 RX_WPTR Receive FIFO Write Pointer Value 16 2 read-only RX_THD Receiver Threshold Register 0x18 32 read-write n 0x0 0x0 RDT Receiver Data Threshold Value 0 4 read-write RNCK_THD Receiver NACK Threshold Value 8 4 read-write 0 Zero Threshold. RTE will not be set #0000 TX_BUF Transmit Data Buffer 0x30 32 read-write n 0x0 0x0 TX_BYTE Transmit Data Byte 0 8 write-only TX_GETU Transmitter Guard ETU Value Register 0x34 32 read-write n 0x0 0x0 GETU Transmitter Guard Time Value in ETU 0 8 read-write 0 no additional ETUs inserted (default) #0 1 1 additional ETU inserted #1 11111110 254 additional ETUs inserted #11111110 11111111 Subtracts one ETU by reducing the number of STOP bits from two to one #11111111 TX_STATUS Transmitter Status Register 0x24 32 read-write n 0x0 0x0 ETCF Early Transmit Complete Flag 4 1 read-write 0 Transmit pending or in progress #0 1 Transmit complete (default) #1 GPCNT0_TO General Purpose Counter 0 Timeout Flag 8 1 read-write 0 GPCNT0_VAL time not reached, or bit has been cleared. (default) #0 1 General Purpose counter has reached the GPCNT0_VAL value #1 GPCNT1_TO General Purpose Counter 1 Timeout Flag 9 1 read-write 0 GPCNT1_VAL time not reached, or bit has been cleared. (default) #0 1 General Purpose counter has reached the GPCNT1_VAL value #1 TCF Transmit Complete Flag 5 1 read-write 0 Transmit pending or in progress #0 1 Transmit complete (default) #1 TDTF Transmit Data Threshold Flag 7 1 read-only 0 Number of bytes in FIFO is greater than TDT[3:0], or bit has been cleared #0 1 Number of bytes in FIFO is less than or equal to TDT[3:0] (default) #1 TFE Transmit FIFO Empty Flag 3 1 read-write 0 Transmit FIFO is not empty #0 1 Transmit FIFO is empty (default) #1 TFF Transmit FIFO Full Flag 6 1 read-write 0 Transmit FIFO Full condition has not occurred (default) #0 1 A Transmit FIFO Full condition has occurred #1 TNTE Transmit NACK Threshold Error Flag 0 1 read-write 0 Transmit NACK threshold has not been reached (default) #0 1 Transmit NACK threshold reached; transmitter frozen #1 TX_CNT Transmit FIFO Byte Count 22 3 read-only 0 FIFO is emtpy #000 TX_RPTR Transmit FIFO Read Pointer 16 2 read-only TX_THD Transmitter Threshold Register 0x1C 32 read-write n 0x0 0x0 TDT Transmitter Data Threshold Value 0 4 read-write TNCK_THD Transmitter NACK Threshold Value 8 4 read-write 0 TNTE will never be set; retransmission after NACK reception is disabled. #0000 1 TNTE will be set after 1 nack is received; 0 retransmissions occurs. #0001 10 TNTE will be set after 2 nacks are received; at most 1 retransmission occurs. #0010 11 TNTE will be set after 3 nacks are received; at most 2 retransmissions occurs. #0011 1111 TNTE will be set after 15 nacks are received; at most 14 retransmissions occurs. #1111 VER_ID Version ID Register 0x0 32 read-only n 0x0 0x0 VER Version ID of the module 0 32 read-only FGPIOA General Purpose Input/Output FGPIO 0x0 0x0 0x18 registers n PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 FGPIOM General Purpose Input/Output FGPIO 0x0 0x0 0x18 registers n PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 FLEXIO0 FLEXIO0 FLEXIO0 0x0 0x0 0x7A0 registers n FLEXIO0 5 CTRL FlexIO Control Register 0x8 32 read-write n 0x0 0x0 DBGE Debug Enable 30 1 read-write 0 FlexIO is disabled in debug modes. #0 1 FlexIO is enabled in debug modes #1 DOZEN Doze Enable 31 1 read-write 0 FlexIO enabled in Doze modes. #0 1 FlexIO disabled in Doze modes. #1 FASTACC Fast Access 2 1 read-write 0 Configures for normal register accesses to FlexIO #0 1 Configures for fast register accesses to FlexIO #1 FLEXEN FlexIO Enable 0 1 read-write 0 FlexIO module is disabled. #0 1 FlexIO module is enabled. #1 SWRST Software Reset 1 1 read-write 0 Software reset is disabled #0 1 Software reset is enabled, all FlexIO registers except the Control Register are reset. #1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 PIN Pin Number 16 8 read-only SHIFTER Shifter Number 0 8 read-only TIMER Timer Number 8 8 read-only TRIGGER Trigger Number 24 8 read-only PIN Pin State Register 0xC 32 read-only n 0x0 0x0 PDI Pin Data Input 0 32 read-only SHIFTBUF0 Shifter Buffer N Register 0x200 32 read-write n 0x0 0x0 SHIFTBUF Shift Buffer 0 32 read-write SHIFTBUF1 Shifter Buffer N Register 0x204 32 read-write n 0x0 0x0 SHIFTBUF Shift Buffer 0 32 read-write SHIFTBUF2 Shifter Buffer N Register 0x208 32 read-write n 0x0 0x0 SHIFTBUF Shift Buffer 0 32 read-write SHIFTBUF3 Shifter Buffer N Register 0x20C 32 read-write n 0x0 0x0 SHIFTBUF Shift Buffer 0 32 read-write SHIFTBUF4 Shifter Buffer N Register 0x210 32 read-write n 0x0 0x0 SHIFTBUF Shift Buffer 0 32 read-write SHIFTBUF5 Shifter Buffer N Register 0x214 32 read-write n 0x0 0x0 SHIFTBUF Shift Buffer 0 32 read-write SHIFTBUF6 Shifter Buffer N Register 0x218 32 read-write n 0x0 0x0 SHIFTBUF Shift Buffer 0 32 read-write SHIFTBUF7 Shifter Buffer N Register 0x21C 32 read-write n 0x0 0x0 SHIFTBUF Shift Buffer 0 32 read-write SHIFTBUFBBS0 Shifter Buffer N Bit Byte Swapped Register 0x380 32 read-write n 0x0 0x0 SHIFTBUFBBS Shift Buffer 0 32 read-write SHIFTBUFBBS1 Shifter Buffer N Bit Byte Swapped Register 0x384 32 read-write n 0x0 0x0 SHIFTBUFBBS Shift Buffer 0 32 read-write SHIFTBUFBBS2 Shifter Buffer N Bit Byte Swapped Register 0x388 32 read-write n 0x0 0x0 SHIFTBUFBBS Shift Buffer 0 32 read-write SHIFTBUFBBS3 Shifter Buffer N Bit Byte Swapped Register 0x38C 32 read-write n 0x0 0x0 SHIFTBUFBBS Shift Buffer 0 32 read-write SHIFTBUFBBS4 Shifter Buffer N Bit Byte Swapped Register 0x390 32 read-write n 0x0 0x0 SHIFTBUFBBS Shift Buffer 0 32 read-write SHIFTBUFBBS5 Shifter Buffer N Bit Byte Swapped Register 0x394 32 read-write n 0x0 0x0 SHIFTBUFBBS Shift Buffer 0 32 read-write SHIFTBUFBBS6 Shifter Buffer N Bit Byte Swapped Register 0x398 32 read-write n 0x0 0x0 SHIFTBUFBBS Shift Buffer 0 32 read-write SHIFTBUFBBS7 Shifter Buffer N Bit Byte Swapped Register 0x39C 32 read-write n 0x0 0x0 SHIFTBUFBBS Shift Buffer 0 32 read-write SHIFTBUFBIS0 Shifter Buffer N Bit Swapped Register 0x280 32 read-write n 0x0 0x0 SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBIS1 Shifter Buffer N Bit Swapped Register 0x284 32 read-write n 0x0 0x0 SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBIS2 Shifter Buffer N Bit Swapped Register 0x288 32 read-write n 0x0 0x0 SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBIS3 Shifter Buffer N Bit Swapped Register 0x28C 32 read-write n 0x0 0x0 SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBIS4 Shifter Buffer N Bit Swapped Register 0x290 32 read-write n 0x0 0x0 SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBIS5 Shifter Buffer N Bit Swapped Register 0x294 32 read-write n 0x0 0x0 SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBIS6 Shifter Buffer N Bit Swapped Register 0x298 32 read-write n 0x0 0x0 SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBIS7 Shifter Buffer N Bit Swapped Register 0x29C 32 read-write n 0x0 0x0 SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBYS0 Shifter Buffer N Byte Swapped Register 0x300 32 read-write n 0x0 0x0 SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFBYS1 Shifter Buffer N Byte Swapped Register 0x304 32 read-write n 0x0 0x0 SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFBYS2 Shifter Buffer N Byte Swapped Register 0x308 32 read-write n 0x0 0x0 SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFBYS3 Shifter Buffer N Byte Swapped Register 0x30C 32 read-write n 0x0 0x0 SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFBYS4 Shifter Buffer N Byte Swapped Register 0x310 32 read-write n 0x0 0x0 SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFBYS5 Shifter Buffer N Byte Swapped Register 0x314 32 read-write n 0x0 0x0 SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFBYS6 Shifter Buffer N Byte Swapped Register 0x318 32 read-write n 0x0 0x0 SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFBYS7 Shifter Buffer N Byte Swapped Register 0x31C 32 read-write n 0x0 0x0 SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFHWS0 Shifter Buffer N Half Word Swapped Register 0x700 32 read-write n 0x0 0x0 SHIFTBUFHWS Shift Buffer 0 32 read-write SHIFTBUFHWS1 Shifter Buffer N Half Word Swapped Register 0x704 32 read-write n 0x0 0x0 SHIFTBUFHWS Shift Buffer 0 32 read-write SHIFTBUFHWS2 Shifter Buffer N Half Word Swapped Register 0x708 32 read-write n 0x0 0x0 SHIFTBUFHWS Shift Buffer 0 32 read-write SHIFTBUFHWS3 Shifter Buffer N Half Word Swapped Register 0x70C 32 read-write n 0x0 0x0 SHIFTBUFHWS Shift Buffer 0 32 read-write SHIFTBUFHWS4 Shifter Buffer N Half Word Swapped Register 0x710 32 read-write n 0x0 0x0 SHIFTBUFHWS Shift Buffer 0 32 read-write SHIFTBUFHWS5 Shifter Buffer N Half Word Swapped Register 0x714 32 read-write n 0x0 0x0 SHIFTBUFHWS Shift Buffer 0 32 read-write SHIFTBUFHWS6 Shifter Buffer N Half Word Swapped Register 0x718 32 read-write n 0x0 0x0 SHIFTBUFHWS Shift Buffer 0 32 read-write SHIFTBUFHWS7 Shifter Buffer N Half Word Swapped Register 0x71C 32 read-write n 0x0 0x0 SHIFTBUFHWS Shift Buffer 0 32 read-write SHIFTBUFNBS0 Shifter Buffer N Nibble Byte Swapped Register 0x680 32 read-write n 0x0 0x0 SHIFTBUFNBS Shift Buffer 0 32 read-write SHIFTBUFNBS1 Shifter Buffer N Nibble Byte Swapped Register 0x684 32 read-write n 0x0 0x0 SHIFTBUFNBS Shift Buffer 0 32 read-write SHIFTBUFNBS2 Shifter Buffer N Nibble Byte Swapped Register 0x688 32 read-write n 0x0 0x0 SHIFTBUFNBS Shift Buffer 0 32 read-write SHIFTBUFNBS3 Shifter Buffer N Nibble Byte Swapped Register 0x68C 32 read-write n 0x0 0x0 SHIFTBUFNBS Shift Buffer 0 32 read-write SHIFTBUFNBS4 Shifter Buffer N Nibble Byte Swapped Register 0x690 32 read-write n 0x0 0x0 SHIFTBUFNBS Shift Buffer 0 32 read-write SHIFTBUFNBS5 Shifter Buffer N Nibble Byte Swapped Register 0x694 32 read-write n 0x0 0x0 SHIFTBUFNBS Shift Buffer 0 32 read-write SHIFTBUFNBS6 Shifter Buffer N Nibble Byte Swapped Register 0x698 32 read-write n 0x0 0x0 SHIFTBUFNBS Shift Buffer 0 32 read-write SHIFTBUFNBS7 Shifter Buffer N Nibble Byte Swapped Register 0x69C 32 read-write n 0x0 0x0 SHIFTBUFNBS Shift Buffer 0 32 read-write SHIFTBUFNIS0 Shifter Buffer N Nibble Swapped Register 0x780 32 read-write n 0x0 0x0 SHIFTBUFNIS Shift Buffer 0 32 read-write SHIFTBUFNIS1 Shifter Buffer N Nibble Swapped Register 0x784 32 read-write n 0x0 0x0 SHIFTBUFNIS Shift Buffer 0 32 read-write SHIFTBUFNIS2 Shifter Buffer N Nibble Swapped Register 0x788 32 read-write n 0x0 0x0 SHIFTBUFNIS Shift Buffer 0 32 read-write SHIFTBUFNIS3 Shifter Buffer N Nibble Swapped Register 0x78C 32 read-write n 0x0 0x0 SHIFTBUFNIS Shift Buffer 0 32 read-write SHIFTBUFNIS4 Shifter Buffer N Nibble Swapped Register 0x790 32 read-write n 0x0 0x0 SHIFTBUFNIS Shift Buffer 0 32 read-write SHIFTBUFNIS5 Shifter Buffer N Nibble Swapped Register 0x794 32 read-write n 0x0 0x0 SHIFTBUFNIS Shift Buffer 0 32 read-write SHIFTBUFNIS6 Shifter Buffer N Nibble Swapped Register 0x798 32 read-write n 0x0 0x0 SHIFTBUFNIS Shift Buffer 0 32 read-write SHIFTBUFNIS7 Shifter Buffer N Nibble Swapped Register 0x79C 32 read-write n 0x0 0x0 SHIFTBUFNIS Shift Buffer 0 32 read-write SHIFTCFG0 Shifter Configuration N Register 0x100 32 read-write n 0x0 0x0 INSRC Input Source 8 1 read-write 0 Pin #0 1 Shifter N+1 Output #1 PWIDTH Parallel Width 16 5 read-write SSTART Shifter Start bit 0 2 read-write 00 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable #00 01 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift #01 10 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 #10 11 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 #11 SSTOP Shifter Stop bit 4 2 read-write 00 Stop bit disabled for transmitter/receiver/match store #00 01 Reserved for transmitter/receiver/match store #01 10 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 #10 11 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 #11 SHIFTCFG1 Shifter Configuration N Register 0x104 32 read-write n 0x0 0x0 INSRC Input Source 8 1 read-write 0 Pin #0 1 Shifter N+1 Output #1 PWIDTH Parallel Width 16 5 read-write SSTART Shifter Start bit 0 2 read-write 00 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable #00 01 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift #01 10 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 #10 11 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 #11 SSTOP Shifter Stop bit 4 2 read-write 00 Stop bit disabled for transmitter/receiver/match store #00 01 Reserved for transmitter/receiver/match store #01 10 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 #10 11 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 #11 SHIFTCFG2 Shifter Configuration N Register 0x108 32 read-write n 0x0 0x0 INSRC Input Source 8 1 read-write 0 Pin #0 1 Shifter N+1 Output #1 PWIDTH Parallel Width 16 5 read-write SSTART Shifter Start bit 0 2 read-write 00 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable #00 01 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift #01 10 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 #10 11 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 #11 SSTOP Shifter Stop bit 4 2 read-write 00 Stop bit disabled for transmitter/receiver/match store #00 01 Reserved for transmitter/receiver/match store #01 10 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 #10 11 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 #11 SHIFTCFG3 Shifter Configuration N Register 0x10C 32 read-write n 0x0 0x0 INSRC Input Source 8 1 read-write 0 Pin #0 1 Shifter N+1 Output #1 PWIDTH Parallel Width 16 5 read-write SSTART Shifter Start bit 0 2 read-write 00 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable #00 01 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift #01 10 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 #10 11 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 #11 SSTOP Shifter Stop bit 4 2 read-write 00 Stop bit disabled for transmitter/receiver/match store #00 01 Reserved for transmitter/receiver/match store #01 10 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 #10 11 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 #11 SHIFTCFG4 Shifter Configuration N Register 0x110 32 read-write n 0x0 0x0 INSRC Input Source 8 1 read-write 0 Pin #0 1 Shifter N+1 Output #1 PWIDTH Parallel Width 16 5 read-write SSTART Shifter Start bit 0 2 read-write 00 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable #00 01 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift #01 10 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 #10 11 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 #11 SSTOP Shifter Stop bit 4 2 read-write 00 Stop bit disabled for transmitter/receiver/match store #00 01 Reserved for transmitter/receiver/match store #01 10 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 #10 11 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 #11 SHIFTCFG5 Shifter Configuration N Register 0x114 32 read-write n 0x0 0x0 INSRC Input Source 8 1 read-write 0 Pin #0 1 Shifter N+1 Output #1 PWIDTH Parallel Width 16 5 read-write SSTART Shifter Start bit 0 2 read-write 00 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable #00 01 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift #01 10 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 #10 11 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 #11 SSTOP Shifter Stop bit 4 2 read-write 00 Stop bit disabled for transmitter/receiver/match store #00 01 Reserved for transmitter/receiver/match store #01 10 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 #10 11 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 #11 SHIFTCFG6 Shifter Configuration N Register 0x118 32 read-write n 0x0 0x0 INSRC Input Source 8 1 read-write 0 Pin #0 1 Shifter N+1 Output #1 PWIDTH Parallel Width 16 5 read-write SSTART Shifter Start bit 0 2 read-write 00 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable #00 01 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift #01 10 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 #10 11 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 #11 SSTOP Shifter Stop bit 4 2 read-write 00 Stop bit disabled for transmitter/receiver/match store #00 01 Reserved for transmitter/receiver/match store #01 10 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 #10 11 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 #11 SHIFTCFG7 Shifter Configuration N Register 0x11C 32 read-write n 0x0 0x0 INSRC Input Source 8 1 read-write 0 Pin #0 1 Shifter N+1 Output #1 PWIDTH Parallel Width 16 5 read-write SSTART Shifter Start bit 0 2 read-write 00 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable #00 01 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift #01 10 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 #10 11 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 #11 SSTOP Shifter Stop bit 4 2 read-write 00 Stop bit disabled for transmitter/receiver/match store #00 01 Reserved for transmitter/receiver/match store #01 10 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 #10 11 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 #11 SHIFTCTL0 Shifter Control N Register 0x80 32 read-write n 0x0 0x0 PINCFG Shifter Pin Configuration 16 2 read-write 00 Shifter pin output disabled #00 01 Shifter pin open drain or bidirectional output enable #01 10 Shifter pin bidirectional output data #10 11 Shifter pin output #11 PINPOL Shifter Pin Polarity 7 1 read-write 0 Pin is active high #0 1 Pin is active low #1 PINSEL Shifter Pin Select 8 5 read-write SMOD Shifter Mode 0 3 read-write 000 Disabled. #000 001 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. #001 010 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. #010 100 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. #100 101 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. #101 TIMPOL Timer Polarity 23 1 read-write 0 Shift on posedge of Shift clock #0 1 Shift on negedge of Shift clock #1 TIMSEL Timer Select 24 3 read-write SHIFTCTL1 Shifter Control N Register 0x84 32 read-write n 0x0 0x0 PINCFG Shifter Pin Configuration 16 2 read-write 00 Shifter pin output disabled #00 01 Shifter pin open drain or bidirectional output enable #01 10 Shifter pin bidirectional output data #10 11 Shifter pin output #11 PINPOL Shifter Pin Polarity 7 1 read-write 0 Pin is active high #0 1 Pin is active low #1 PINSEL Shifter Pin Select 8 5 read-write SMOD Shifter Mode 0 3 read-write 000 Disabled. #000 001 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. #001 010 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. #010 100 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. #100 101 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. #101 TIMPOL Timer Polarity 23 1 read-write 0 Shift on posedge of Shift clock #0 1 Shift on negedge of Shift clock #1 TIMSEL Timer Select 24 3 read-write SHIFTCTL2 Shifter Control N Register 0x88 32 read-write n 0x0 0x0 PINCFG Shifter Pin Configuration 16 2 read-write 00 Shifter pin output disabled #00 01 Shifter pin open drain or bidirectional output enable #01 10 Shifter pin bidirectional output data #10 11 Shifter pin output #11 PINPOL Shifter Pin Polarity 7 1 read-write 0 Pin is active high #0 1 Pin is active low #1 PINSEL Shifter Pin Select 8 5 read-write SMOD Shifter Mode 0 3 read-write 000 Disabled. #000 001 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. #001 010 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. #010 100 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. #100 101 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. #101 TIMPOL Timer Polarity 23 1 read-write 0 Shift on posedge of Shift clock #0 1 Shift on negedge of Shift clock #1 TIMSEL Timer Select 24 3 read-write SHIFTCTL3 Shifter Control N Register 0x8C 32 read-write n 0x0 0x0 PINCFG Shifter Pin Configuration 16 2 read-write 00 Shifter pin output disabled #00 01 Shifter pin open drain or bidirectional output enable #01 10 Shifter pin bidirectional output data #10 11 Shifter pin output #11 PINPOL Shifter Pin Polarity 7 1 read-write 0 Pin is active high #0 1 Pin is active low #1 PINSEL Shifter Pin Select 8 5 read-write SMOD Shifter Mode 0 3 read-write 000 Disabled. #000 001 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. #001 010 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. #010 100 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. #100 101 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. #101 TIMPOL Timer Polarity 23 1 read-write 0 Shift on posedge of Shift clock #0 1 Shift on negedge of Shift clock #1 TIMSEL Timer Select 24 3 read-write SHIFTCTL4 Shifter Control N Register 0x90 32 read-write n 0x0 0x0 PINCFG Shifter Pin Configuration 16 2 read-write 00 Shifter pin output disabled #00 01 Shifter pin open drain or bidirectional output enable #01 10 Shifter pin bidirectional output data #10 11 Shifter pin output #11 PINPOL Shifter Pin Polarity 7 1 read-write 0 Pin is active high #0 1 Pin is active low #1 PINSEL Shifter Pin Select 8 5 read-write SMOD Shifter Mode 0 3 read-write 000 Disabled. #000 001 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. #001 010 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. #010 100 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. #100 101 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. #101 TIMPOL Timer Polarity 23 1 read-write 0 Shift on posedge of Shift clock #0 1 Shift on negedge of Shift clock #1 TIMSEL Timer Select 24 3 read-write SHIFTCTL5 Shifter Control N Register 0x94 32 read-write n 0x0 0x0 PINCFG Shifter Pin Configuration 16 2 read-write 00 Shifter pin output disabled #00 01 Shifter pin open drain or bidirectional output enable #01 10 Shifter pin bidirectional output data #10 11 Shifter pin output #11 PINPOL Shifter Pin Polarity 7 1 read-write 0 Pin is active high #0 1 Pin is active low #1 PINSEL Shifter Pin Select 8 5 read-write SMOD Shifter Mode 0 3 read-write 000 Disabled. #000 001 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. #001 010 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. #010 100 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. #100 101 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. #101 TIMPOL Timer Polarity 23 1 read-write 0 Shift on posedge of Shift clock #0 1 Shift on negedge of Shift clock #1 TIMSEL Timer Select 24 3 read-write SHIFTCTL6 Shifter Control N Register 0x98 32 read-write n 0x0 0x0 PINCFG Shifter Pin Configuration 16 2 read-write 00 Shifter pin output disabled #00 01 Shifter pin open drain or bidirectional output enable #01 10 Shifter pin bidirectional output data #10 11 Shifter pin output #11 PINPOL Shifter Pin Polarity 7 1 read-write 0 Pin is active high #0 1 Pin is active low #1 PINSEL Shifter Pin Select 8 5 read-write SMOD Shifter Mode 0 3 read-write 000 Disabled. #000 001 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. #001 010 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. #010 100 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. #100 101 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. #101 TIMPOL Timer Polarity 23 1 read-write 0 Shift on posedge of Shift clock #0 1 Shift on negedge of Shift clock #1 TIMSEL Timer Select 24 3 read-write SHIFTCTL7 Shifter Control N Register 0x9C 32 read-write n 0x0 0x0 PINCFG Shifter Pin Configuration 16 2 read-write 00 Shifter pin output disabled #00 01 Shifter pin open drain or bidirectional output enable #01 10 Shifter pin bidirectional output data #10 11 Shifter pin output #11 PINPOL Shifter Pin Polarity 7 1 read-write 0 Pin is active high #0 1 Pin is active low #1 PINSEL Shifter Pin Select 8 5 read-write SMOD Shifter Mode 0 3 read-write 000 Disabled. #000 001 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. #001 010 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. #010 100 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. #100 101 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. #101 TIMPOL Timer Polarity 23 1 read-write 0 Shift on posedge of Shift clock #0 1 Shift on negedge of Shift clock #1 TIMSEL Timer Select 24 3 read-write SHIFTEIEN Shifter Error Interrupt Enable 0x24 32 read-write n 0x0 0x0 SEIE Shifter Error Interrupt Enable 0 8 read-write 0 Shifter Error Flag interrupt disabled #0 1 Shifter Error Flag interrupt enabled #1 SHIFTERR Shifter Error Register 0x14 32 read-write n 0x0 0x0 SEF Shifter Error Flags 0 8 read-write 0 Shifter Error Flag is clear #0 1 Shifter Error Flag is set #1 SHIFTSDEN Shifter Status DMA Enable 0x30 32 read-write n 0x0 0x0 SSDE Shifter Status DMA Enable 0 8 read-write 0 Shifter Status Flag DMA request is disabled #0 1 Shifter Status Flag DMA request is enabled #1 SHIFTSIEN Shifter Status Interrupt Enable 0x20 32 read-write n 0x0 0x0 SSIE Shifter Status Interrupt Enable 0 8 read-write 0 Shifter Status Flag interrupt disabled #0 1 Shifter Status Flag interrupt enabled #1 SHIFTSTAT Shifter Status Register 0x10 32 read-write n 0x0 0x0 SSF Shifter Status Flag 0 8 read-write 0 Status flag is clear #0 1 Status flag is set #1 SHIFTSTATE Shifter State Register 0x40 32 read-write n 0x0 0x0 STATE Current State Pointer 0 3 read-write TIMCFG0 Timer Configuration N Register 0x480 32 read-write n 0x0 0x0 TIMDEC Timer Decrement 20 2 read-write 00 Decrement counter on FlexIO clock, Shift clock equals Timer output. #00 01 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. #01 10 Decrement counter on Pin input (both edges), Shift clock equals Pin input. #10 11 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. #11 TIMDIS Timer Disable 12 3 read-write 000 Timer never disabled #000 001 Timer disabled on Timer N-1 disable #001 010 Timer disabled on Timer compare #010 011 Timer disabled on Timer compare and Trigger Low #011 100 Timer disabled on Pin rising or falling edge #100 101 Timer disabled on Pin rising or falling edge provided Trigger is high #101 110 Timer disabled on Trigger falling edge #110 TIMENA Timer Enable 8 3 read-write 000 Timer always enabled #000 001 Timer enabled on Timer N-1 enable #001 010 Timer enabled on Trigger high #010 011 Timer enabled on Trigger high and Pin high #011 100 Timer enabled on Pin rising edge #100 101 Timer enabled on Pin rising edge and Trigger high #101 110 Timer enabled on Trigger rising edge #110 111 Timer enabled on Trigger rising or falling edge #111 TIMOUT Timer Output 24 2 read-write 00 Timer output is logic one when enabled and is not affected by timer reset #00 01 Timer output is logic zero when enabled and is not affected by timer reset #01 10 Timer output is logic one when enabled and on timer reset #10 11 Timer output is logic zero when enabled and on timer reset #11 TIMRST Timer Reset 16 3 read-write 000 Timer never reset #000 010 Timer reset on Timer Pin equal to Timer Output #010 011 Timer reset on Timer Trigger equal to Timer Output #011 100 Timer reset on Timer Pin rising edge #100 110 Timer reset on Trigger rising edge #110 111 Timer reset on Trigger rising or falling edge #111 TSTART Timer Start Bit 1 1 read-write 0 Start bit disabled #0 1 Start bit enabled #1 TSTOP Timer Stop Bit 4 2 read-write 00 Stop bit disabled #00 01 Stop bit is enabled on timer compare #01 10 Stop bit is enabled on timer disable #10 11 Stop bit is enabled on timer compare and timer disable #11 TIMCFG1 Timer Configuration N Register 0x484 32 read-write n 0x0 0x0 TIMDEC Timer Decrement 20 2 read-write 00 Decrement counter on FlexIO clock, Shift clock equals Timer output. #00 01 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. #01 10 Decrement counter on Pin input (both edges), Shift clock equals Pin input. #10 11 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. #11 TIMDIS Timer Disable 12 3 read-write 000 Timer never disabled #000 001 Timer disabled on Timer N-1 disable #001 010 Timer disabled on Timer compare #010 011 Timer disabled on Timer compare and Trigger Low #011 100 Timer disabled on Pin rising or falling edge #100 101 Timer disabled on Pin rising or falling edge provided Trigger is high #101 110 Timer disabled on Trigger falling edge #110 TIMENA Timer Enable 8 3 read-write 000 Timer always enabled #000 001 Timer enabled on Timer N-1 enable #001 010 Timer enabled on Trigger high #010 011 Timer enabled on Trigger high and Pin high #011 100 Timer enabled on Pin rising edge #100 101 Timer enabled on Pin rising edge and Trigger high #101 110 Timer enabled on Trigger rising edge #110 111 Timer enabled on Trigger rising or falling edge #111 TIMOUT Timer Output 24 2 read-write 00 Timer output is logic one when enabled and is not affected by timer reset #00 01 Timer output is logic zero when enabled and is not affected by timer reset #01 10 Timer output is logic one when enabled and on timer reset #10 11 Timer output is logic zero when enabled and on timer reset #11 TIMRST Timer Reset 16 3 read-write 000 Timer never reset #000 010 Timer reset on Timer Pin equal to Timer Output #010 011 Timer reset on Timer Trigger equal to Timer Output #011 100 Timer reset on Timer Pin rising edge #100 110 Timer reset on Trigger rising edge #110 111 Timer reset on Trigger rising or falling edge #111 TSTART Timer Start Bit 1 1 read-write 0 Start bit disabled #0 1 Start bit enabled #1 TSTOP Timer Stop Bit 4 2 read-write 00 Stop bit disabled #00 01 Stop bit is enabled on timer compare #01 10 Stop bit is enabled on timer disable #10 11 Stop bit is enabled on timer compare and timer disable #11 TIMCFG2 Timer Configuration N Register 0x488 32 read-write n 0x0 0x0 TIMDEC Timer Decrement 20 2 read-write 00 Decrement counter on FlexIO clock, Shift clock equals Timer output. #00 01 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. #01 10 Decrement counter on Pin input (both edges), Shift clock equals Pin input. #10 11 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. #11 TIMDIS Timer Disable 12 3 read-write 000 Timer never disabled #000 001 Timer disabled on Timer N-1 disable #001 010 Timer disabled on Timer compare #010 011 Timer disabled on Timer compare and Trigger Low #011 100 Timer disabled on Pin rising or falling edge #100 101 Timer disabled on Pin rising or falling edge provided Trigger is high #101 110 Timer disabled on Trigger falling edge #110 TIMENA Timer Enable 8 3 read-write 000 Timer always enabled #000 001 Timer enabled on Timer N-1 enable #001 010 Timer enabled on Trigger high #010 011 Timer enabled on Trigger high and Pin high #011 100 Timer enabled on Pin rising edge #100 101 Timer enabled on Pin rising edge and Trigger high #101 110 Timer enabled on Trigger rising edge #110 111 Timer enabled on Trigger rising or falling edge #111 TIMOUT Timer Output 24 2 read-write 00 Timer output is logic one when enabled and is not affected by timer reset #00 01 Timer output is logic zero when enabled and is not affected by timer reset #01 10 Timer output is logic one when enabled and on timer reset #10 11 Timer output is logic zero when enabled and on timer reset #11 TIMRST Timer Reset 16 3 read-write 000 Timer never reset #000 010 Timer reset on Timer Pin equal to Timer Output #010 011 Timer reset on Timer Trigger equal to Timer Output #011 100 Timer reset on Timer Pin rising edge #100 110 Timer reset on Trigger rising edge #110 111 Timer reset on Trigger rising or falling edge #111 TSTART Timer Start Bit 1 1 read-write 0 Start bit disabled #0 1 Start bit enabled #1 TSTOP Timer Stop Bit 4 2 read-write 00 Stop bit disabled #00 01 Stop bit is enabled on timer compare #01 10 Stop bit is enabled on timer disable #10 11 Stop bit is enabled on timer compare and timer disable #11 TIMCFG3 Timer Configuration N Register 0x48C 32 read-write n 0x0 0x0 TIMDEC Timer Decrement 20 2 read-write 00 Decrement counter on FlexIO clock, Shift clock equals Timer output. #00 01 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. #01 10 Decrement counter on Pin input (both edges), Shift clock equals Pin input. #10 11 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. #11 TIMDIS Timer Disable 12 3 read-write 000 Timer never disabled #000 001 Timer disabled on Timer N-1 disable #001 010 Timer disabled on Timer compare #010 011 Timer disabled on Timer compare and Trigger Low #011 100 Timer disabled on Pin rising or falling edge #100 101 Timer disabled on Pin rising or falling edge provided Trigger is high #101 110 Timer disabled on Trigger falling edge #110 TIMENA Timer Enable 8 3 read-write 000 Timer always enabled #000 001 Timer enabled on Timer N-1 enable #001 010 Timer enabled on Trigger high #010 011 Timer enabled on Trigger high and Pin high #011 100 Timer enabled on Pin rising edge #100 101 Timer enabled on Pin rising edge and Trigger high #101 110 Timer enabled on Trigger rising edge #110 111 Timer enabled on Trigger rising or falling edge #111 TIMOUT Timer Output 24 2 read-write 00 Timer output is logic one when enabled and is not affected by timer reset #00 01 Timer output is logic zero when enabled and is not affected by timer reset #01 10 Timer output is logic one when enabled and on timer reset #10 11 Timer output is logic zero when enabled and on timer reset #11 TIMRST Timer Reset 16 3 read-write 000 Timer never reset #000 010 Timer reset on Timer Pin equal to Timer Output #010 011 Timer reset on Timer Trigger equal to Timer Output #011 100 Timer reset on Timer Pin rising edge #100 110 Timer reset on Trigger rising edge #110 111 Timer reset on Trigger rising or falling edge #111 TSTART Timer Start Bit 1 1 read-write 0 Start bit disabled #0 1 Start bit enabled #1 TSTOP Timer Stop Bit 4 2 read-write 00 Stop bit disabled #00 01 Stop bit is enabled on timer compare #01 10 Stop bit is enabled on timer disable #10 11 Stop bit is enabled on timer compare and timer disable #11 TIMCFG4 Timer Configuration N Register 0x490 32 read-write n 0x0 0x0 TIMDEC Timer Decrement 20 2 read-write 00 Decrement counter on FlexIO clock, Shift clock equals Timer output. #00 01 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. #01 10 Decrement counter on Pin input (both edges), Shift clock equals Pin input. #10 11 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. #11 TIMDIS Timer Disable 12 3 read-write 000 Timer never disabled #000 001 Timer disabled on Timer N-1 disable #001 010 Timer disabled on Timer compare #010 011 Timer disabled on Timer compare and Trigger Low #011 100 Timer disabled on Pin rising or falling edge #100 101 Timer disabled on Pin rising or falling edge provided Trigger is high #101 110 Timer disabled on Trigger falling edge #110 TIMENA Timer Enable 8 3 read-write 000 Timer always enabled #000 001 Timer enabled on Timer N-1 enable #001 010 Timer enabled on Trigger high #010 011 Timer enabled on Trigger high and Pin high #011 100 Timer enabled on Pin rising edge #100 101 Timer enabled on Pin rising edge and Trigger high #101 110 Timer enabled on Trigger rising edge #110 111 Timer enabled on Trigger rising or falling edge #111 TIMOUT Timer Output 24 2 read-write 00 Timer output is logic one when enabled and is not affected by timer reset #00 01 Timer output is logic zero when enabled and is not affected by timer reset #01 10 Timer output is logic one when enabled and on timer reset #10 11 Timer output is logic zero when enabled and on timer reset #11 TIMRST Timer Reset 16 3 read-write 000 Timer never reset #000 010 Timer reset on Timer Pin equal to Timer Output #010 011 Timer reset on Timer Trigger equal to Timer Output #011 100 Timer reset on Timer Pin rising edge #100 110 Timer reset on Trigger rising edge #110 111 Timer reset on Trigger rising or falling edge #111 TSTART Timer Start Bit 1 1 read-write 0 Start bit disabled #0 1 Start bit enabled #1 TSTOP Timer Stop Bit 4 2 read-write 00 Stop bit disabled #00 01 Stop bit is enabled on timer compare #01 10 Stop bit is enabled on timer disable #10 11 Stop bit is enabled on timer compare and timer disable #11 TIMCFG5 Timer Configuration N Register 0x494 32 read-write n 0x0 0x0 TIMDEC Timer Decrement 20 2 read-write 00 Decrement counter on FlexIO clock, Shift clock equals Timer output. #00 01 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. #01 10 Decrement counter on Pin input (both edges), Shift clock equals Pin input. #10 11 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. #11 TIMDIS Timer Disable 12 3 read-write 000 Timer never disabled #000 001 Timer disabled on Timer N-1 disable #001 010 Timer disabled on Timer compare #010 011 Timer disabled on Timer compare and Trigger Low #011 100 Timer disabled on Pin rising or falling edge #100 101 Timer disabled on Pin rising or falling edge provided Trigger is high #101 110 Timer disabled on Trigger falling edge #110 TIMENA Timer Enable 8 3 read-write 000 Timer always enabled #000 001 Timer enabled on Timer N-1 enable #001 010 Timer enabled on Trigger high #010 011 Timer enabled on Trigger high and Pin high #011 100 Timer enabled on Pin rising edge #100 101 Timer enabled on Pin rising edge and Trigger high #101 110 Timer enabled on Trigger rising edge #110 111 Timer enabled on Trigger rising or falling edge #111 TIMOUT Timer Output 24 2 read-write 00 Timer output is logic one when enabled and is not affected by timer reset #00 01 Timer output is logic zero when enabled and is not affected by timer reset #01 10 Timer output is logic one when enabled and on timer reset #10 11 Timer output is logic zero when enabled and on timer reset #11 TIMRST Timer Reset 16 3 read-write 000 Timer never reset #000 010 Timer reset on Timer Pin equal to Timer Output #010 011 Timer reset on Timer Trigger equal to Timer Output #011 100 Timer reset on Timer Pin rising edge #100 110 Timer reset on Trigger rising edge #110 111 Timer reset on Trigger rising or falling edge #111 TSTART Timer Start Bit 1 1 read-write 0 Start bit disabled #0 1 Start bit enabled #1 TSTOP Timer Stop Bit 4 2 read-write 00 Stop bit disabled #00 01 Stop bit is enabled on timer compare #01 10 Stop bit is enabled on timer disable #10 11 Stop bit is enabled on timer compare and timer disable #11 TIMCFG6 Timer Configuration N Register 0x498 32 read-write n 0x0 0x0 TIMDEC Timer Decrement 20 2 read-write 00 Decrement counter on FlexIO clock, Shift clock equals Timer output. #00 01 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. #01 10 Decrement counter on Pin input (both edges), Shift clock equals Pin input. #10 11 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. #11 TIMDIS Timer Disable 12 3 read-write 000 Timer never disabled #000 001 Timer disabled on Timer N-1 disable #001 010 Timer disabled on Timer compare #010 011 Timer disabled on Timer compare and Trigger Low #011 100 Timer disabled on Pin rising or falling edge #100 101 Timer disabled on Pin rising or falling edge provided Trigger is high #101 110 Timer disabled on Trigger falling edge #110 TIMENA Timer Enable 8 3 read-write 000 Timer always enabled #000 001 Timer enabled on Timer N-1 enable #001 010 Timer enabled on Trigger high #010 011 Timer enabled on Trigger high and Pin high #011 100 Timer enabled on Pin rising edge #100 101 Timer enabled on Pin rising edge and Trigger high #101 110 Timer enabled on Trigger rising edge #110 111 Timer enabled on Trigger rising or falling edge #111 TIMOUT Timer Output 24 2 read-write 00 Timer output is logic one when enabled and is not affected by timer reset #00 01 Timer output is logic zero when enabled and is not affected by timer reset #01 10 Timer output is logic one when enabled and on timer reset #10 11 Timer output is logic zero when enabled and on timer reset #11 TIMRST Timer Reset 16 3 read-write 000 Timer never reset #000 010 Timer reset on Timer Pin equal to Timer Output #010 011 Timer reset on Timer Trigger equal to Timer Output #011 100 Timer reset on Timer Pin rising edge #100 110 Timer reset on Trigger rising edge #110 111 Timer reset on Trigger rising or falling edge #111 TSTART Timer Start Bit 1 1 read-write 0 Start bit disabled #0 1 Start bit enabled #1 TSTOP Timer Stop Bit 4 2 read-write 00 Stop bit disabled #00 01 Stop bit is enabled on timer compare #01 10 Stop bit is enabled on timer disable #10 11 Stop bit is enabled on timer compare and timer disable #11 TIMCFG7 Timer Configuration N Register 0x49C 32 read-write n 0x0 0x0 TIMDEC Timer Decrement 20 2 read-write 00 Decrement counter on FlexIO clock, Shift clock equals Timer output. #00 01 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. #01 10 Decrement counter on Pin input (both edges), Shift clock equals Pin input. #10 11 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. #11 TIMDIS Timer Disable 12 3 read-write 000 Timer never disabled #000 001 Timer disabled on Timer N-1 disable #001 010 Timer disabled on Timer compare #010 011 Timer disabled on Timer compare and Trigger Low #011 100 Timer disabled on Pin rising or falling edge #100 101 Timer disabled on Pin rising or falling edge provided Trigger is high #101 110 Timer disabled on Trigger falling edge #110 TIMENA Timer Enable 8 3 read-write 000 Timer always enabled #000 001 Timer enabled on Timer N-1 enable #001 010 Timer enabled on Trigger high #010 011 Timer enabled on Trigger high and Pin high #011 100 Timer enabled on Pin rising edge #100 101 Timer enabled on Pin rising edge and Trigger high #101 110 Timer enabled on Trigger rising edge #110 111 Timer enabled on Trigger rising or falling edge #111 TIMOUT Timer Output 24 2 read-write 00 Timer output is logic one when enabled and is not affected by timer reset #00 01 Timer output is logic zero when enabled and is not affected by timer reset #01 10 Timer output is logic one when enabled and on timer reset #10 11 Timer output is logic zero when enabled and on timer reset #11 TIMRST Timer Reset 16 3 read-write 000 Timer never reset #000 010 Timer reset on Timer Pin equal to Timer Output #010 011 Timer reset on Timer Trigger equal to Timer Output #011 100 Timer reset on Timer Pin rising edge #100 110 Timer reset on Trigger rising edge #110 111 Timer reset on Trigger rising or falling edge #111 TSTART Timer Start Bit 1 1 read-write 0 Start bit disabled #0 1 Start bit enabled #1 TSTOP Timer Stop Bit 4 2 read-write 00 Stop bit disabled #00 01 Stop bit is enabled on timer compare #01 10 Stop bit is enabled on timer disable #10 11 Stop bit is enabled on timer compare and timer disable #11 TIMCMP0 Timer Compare N Register 0x500 32 read-write n 0x0 0x0 CMP Timer Compare Value 0 16 read-write TIMCMP1 Timer Compare N Register 0x504 32 read-write n 0x0 0x0 CMP Timer Compare Value 0 16 read-write TIMCMP2 Timer Compare N Register 0x508 32 read-write n 0x0 0x0 CMP Timer Compare Value 0 16 read-write TIMCMP3 Timer Compare N Register 0x50C 32 read-write n 0x0 0x0 CMP Timer Compare Value 0 16 read-write TIMCMP4 Timer Compare N Register 0x510 32 read-write n 0x0 0x0 CMP Timer Compare Value 0 16 read-write TIMCMP5 Timer Compare N Register 0x514 32 read-write n 0x0 0x0 CMP Timer Compare Value 0 16 read-write TIMCMP6 Timer Compare N Register 0x518 32 read-write n 0x0 0x0 CMP Timer Compare Value 0 16 read-write TIMCMP7 Timer Compare N Register 0x51C 32 read-write n 0x0 0x0 CMP Timer Compare Value 0 16 read-write TIMCTL0 Timer Control N Register 0x400 32 read-write n 0x0 0x0 PINCFG Timer Pin Configuration 16 2 read-write 00 Timer pin output disabled #00 01 Timer pin open drain or bidirectional output enable #01 10 Timer pin bidirectional output data #10 11 Timer pin output #11 PINPOL Timer Pin Polarity 7 1 read-write 0 Pin is active high #0 1 Pin is active low #1 PINSEL Timer Pin Select 8 5 read-write TIMOD Timer Mode 0 2 read-write 00 Timer Disabled. #00 01 Dual 8-bit counters baud/bit mode. #01 10 Dual 8-bit counters PWM mode. #10 11 Single 16-bit counter mode. #11 TRGPOL Trigger Polarity 23 1 read-write 0 Trigger active high #0 1 Trigger active low #1 TRGSEL Trigger Select 24 6 read-write TRGSRC Trigger Source 22 1 read-write 0 External trigger selected #0 1 Internal trigger selected #1 TIMCTL1 Timer Control N Register 0x404 32 read-write n 0x0 0x0 PINCFG Timer Pin Configuration 16 2 read-write 00 Timer pin output disabled #00 01 Timer pin open drain or bidirectional output enable #01 10 Timer pin bidirectional output data #10 11 Timer pin output #11 PINPOL Timer Pin Polarity 7 1 read-write 0 Pin is active high #0 1 Pin is active low #1 PINSEL Timer Pin Select 8 5 read-write TIMOD Timer Mode 0 2 read-write 00 Timer Disabled. #00 01 Dual 8-bit counters baud/bit mode. #01 10 Dual 8-bit counters PWM mode. #10 11 Single 16-bit counter mode. #11 TRGPOL Trigger Polarity 23 1 read-write 0 Trigger active high #0 1 Trigger active low #1 TRGSEL Trigger Select 24 6 read-write TRGSRC Trigger Source 22 1 read-write 0 External trigger selected #0 1 Internal trigger selected #1 TIMCTL2 Timer Control N Register 0x408 32 read-write n 0x0 0x0 PINCFG Timer Pin Configuration 16 2 read-write 00 Timer pin output disabled #00 01 Timer pin open drain or bidirectional output enable #01 10 Timer pin bidirectional output data #10 11 Timer pin output #11 PINPOL Timer Pin Polarity 7 1 read-write 0 Pin is active high #0 1 Pin is active low #1 PINSEL Timer Pin Select 8 5 read-write TIMOD Timer Mode 0 2 read-write 00 Timer Disabled. #00 01 Dual 8-bit counters baud/bit mode. #01 10 Dual 8-bit counters PWM mode. #10 11 Single 16-bit counter mode. #11 TRGPOL Trigger Polarity 23 1 read-write 0 Trigger active high #0 1 Trigger active low #1 TRGSEL Trigger Select 24 6 read-write TRGSRC Trigger Source 22 1 read-write 0 External trigger selected #0 1 Internal trigger selected #1 TIMCTL3 Timer Control N Register 0x40C 32 read-write n 0x0 0x0 PINCFG Timer Pin Configuration 16 2 read-write 00 Timer pin output disabled #00 01 Timer pin open drain or bidirectional output enable #01 10 Timer pin bidirectional output data #10 11 Timer pin output #11 PINPOL Timer Pin Polarity 7 1 read-write 0 Pin is active high #0 1 Pin is active low #1 PINSEL Timer Pin Select 8 5 read-write TIMOD Timer Mode 0 2 read-write 00 Timer Disabled. #00 01 Dual 8-bit counters baud/bit mode. #01 10 Dual 8-bit counters PWM mode. #10 11 Single 16-bit counter mode. #11 TRGPOL Trigger Polarity 23 1 read-write 0 Trigger active high #0 1 Trigger active low #1 TRGSEL Trigger Select 24 6 read-write TRGSRC Trigger Source 22 1 read-write 0 External trigger selected #0 1 Internal trigger selected #1 TIMCTL4 Timer Control N Register 0x410 32 read-write n 0x0 0x0 PINCFG Timer Pin Configuration 16 2 read-write 00 Timer pin output disabled #00 01 Timer pin open drain or bidirectional output enable #01 10 Timer pin bidirectional output data #10 11 Timer pin output #11 PINPOL Timer Pin Polarity 7 1 read-write 0 Pin is active high #0 1 Pin is active low #1 PINSEL Timer Pin Select 8 5 read-write TIMOD Timer Mode 0 2 read-write 00 Timer Disabled. #00 01 Dual 8-bit counters baud/bit mode. #01 10 Dual 8-bit counters PWM mode. #10 11 Single 16-bit counter mode. #11 TRGPOL Trigger Polarity 23 1 read-write 0 Trigger active high #0 1 Trigger active low #1 TRGSEL Trigger Select 24 6 read-write TRGSRC Trigger Source 22 1 read-write 0 External trigger selected #0 1 Internal trigger selected #1 TIMCTL5 Timer Control N Register 0x414 32 read-write n 0x0 0x0 PINCFG Timer Pin Configuration 16 2 read-write 00 Timer pin output disabled #00 01 Timer pin open drain or bidirectional output enable #01 10 Timer pin bidirectional output data #10 11 Timer pin output #11 PINPOL Timer Pin Polarity 7 1 read-write 0 Pin is active high #0 1 Pin is active low #1 PINSEL Timer Pin Select 8 5 read-write TIMOD Timer Mode 0 2 read-write 00 Timer Disabled. #00 01 Dual 8-bit counters baud/bit mode. #01 10 Dual 8-bit counters PWM mode. #10 11 Single 16-bit counter mode. #11 TRGPOL Trigger Polarity 23 1 read-write 0 Trigger active high #0 1 Trigger active low #1 TRGSEL Trigger Select 24 6 read-write TRGSRC Trigger Source 22 1 read-write 0 External trigger selected #0 1 Internal trigger selected #1 TIMCTL6 Timer Control N Register 0x418 32 read-write n 0x0 0x0 PINCFG Timer Pin Configuration 16 2 read-write 00 Timer pin output disabled #00 01 Timer pin open drain or bidirectional output enable #01 10 Timer pin bidirectional output data #10 11 Timer pin output #11 PINPOL Timer Pin Polarity 7 1 read-write 0 Pin is active high #0 1 Pin is active low #1 PINSEL Timer Pin Select 8 5 read-write TIMOD Timer Mode 0 2 read-write 00 Timer Disabled. #00 01 Dual 8-bit counters baud/bit mode. #01 10 Dual 8-bit counters PWM mode. #10 11 Single 16-bit counter mode. #11 TRGPOL Trigger Polarity 23 1 read-write 0 Trigger active high #0 1 Trigger active low #1 TRGSEL Trigger Select 24 6 read-write TRGSRC Trigger Source 22 1 read-write 0 External trigger selected #0 1 Internal trigger selected #1 TIMCTL7 Timer Control N Register 0x41C 32 read-write n 0x0 0x0 PINCFG Timer Pin Configuration 16 2 read-write 00 Timer pin output disabled #00 01 Timer pin open drain or bidirectional output enable #01 10 Timer pin bidirectional output data #10 11 Timer pin output #11 PINPOL Timer Pin Polarity 7 1 read-write 0 Pin is active high #0 1 Pin is active low #1 PINSEL Timer Pin Select 8 5 read-write TIMOD Timer Mode 0 2 read-write 00 Timer Disabled. #00 01 Dual 8-bit counters baud/bit mode. #01 10 Dual 8-bit counters PWM mode. #10 11 Single 16-bit counter mode. #11 TRGPOL Trigger Polarity 23 1 read-write 0 Trigger active high #0 1 Trigger active low #1 TRGSEL Trigger Select 24 6 read-write TRGSRC Trigger Source 22 1 read-write 0 External trigger selected #0 1 Internal trigger selected #1 TIMIEN Timer Interrupt Enable Register 0x28 32 read-write n 0x0 0x0 TEIE Timer Status Interrupt Enable 0 8 read-write 0 Timer Status Flag interrupt is disabled #0 1 Timer Status Flag interrupt is enabled #1 TIMSTAT Timer Status Register 0x18 32 read-write n 0x0 0x0 TSF Timer Status Flags 0 8 read-write 0 Timer Status Flag is clear #0 1 Timer Status Flag is set #1 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Specification Number 0 16 read-only 0x0 Standard features implemented. #0 0x1 Supports state, logic and parallel modes. #1 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only FTFA Flash Memory Interface FTFA 0x0 0x0 0x2C registers n FTFA 42 FACSN Flash Access Segment Number Register 0x2B 8 read-only n 0x0 0x0 NUMSG Number of Segments Indicator 0 8 read-only 100000 Program flash memory is divided into 32 segments (64 Kbytes, 128 Kbytes) #100000 1000000 Program flash memory is divided into 64 segments (256 Kbytes, 512 Kbytes) #1000000 101000 Program flash memory is divided into 40 segments (160 Kbytes) #101000 FACSS Flash Access Segment Size Register 0x28 8 read-only n 0x0 0x0 SGSIZE Segment Size 0 8 read-only FCCOB0 Flash Common Command Object Registers 0x1A 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOB1 Flash Common Command Object Registers 0x13 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOB2 Flash Common Command Object Registers 0xD 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOB3 Flash Common Command Object Registers 0x8 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOB4 Flash Common Command Object Registers 0x40 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOB5 Flash Common Command Object Registers 0x35 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOB6 Flash Common Command Object Registers 0x2B 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOB7 Flash Common Command Object Registers 0x22 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOB8 Flash Common Command Object Registers 0x76 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOB9 Flash Common Command Object Registers 0x67 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOBA Flash Common Command Object Registers 0x59 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCCOBB Flash Common Command Object Registers 0x4C 8 read-write n 0x0 0x0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller 0 8 read-write FCNFG Flash Configuration Register 0x1 8 read-write n 0x0 0x0 CCIE Command Complete Interrupt Enable 7 1 read-write 0 Command complete interrupt disabled #0 1 Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. #1 ERSAREQ Erase All Request 5 1 read-only 0 No request or request complete #0 1 Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state. #1 ERSSUSP Erase Suspend 4 1 read-write 0 No suspend requested #0 1 Suspend the current Erase Flash Sector command execution. #1 RDCOLLIE Read Collision Error Interrupt Enable 6 1 read-write 0 Read collision error interrupt disabled #0 1 Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]). #1 FOPT Flash Option Register 0x3 8 read-only n 0x0 0x0 OPT Nonvolatile Option 0 8 read-only FPROT0 Program Flash Protection Registers 0x56 8 read-write n 0x0 0x0 PROT Program Flash Region Protect 0 8 read-write 0 Program flash region is protected. #0 1 Program flash region is not protected #1 FPROT1 Program Flash Protection Registers 0x43 8 read-write n 0x0 0x0 PROT Program Flash Region Protect 0 8 read-write 0 Program flash region is protected. #0 1 Program flash region is not protected #1 FPROT2 Program Flash Protection Registers 0x31 8 read-write n 0x0 0x0 PROT Program Flash Region Protect 0 8 read-write 0 Program flash region is protected. #0 1 Program flash region is not protected #1 FPROT3 Program Flash Protection Registers 0x20 8 read-write n 0x0 0x0 PROT Program Flash Region Protect 0 8 read-write 0 Program flash region is protected. #0 1 Program flash region is not protected #1 FSEC Flash Security Register 0x2 8 read-only n 0x0 0x0 FSLACC Freescale Failure Analysis Access Code 2 2 read-only 00 Freescale factory access granted #00 01 Freescale factory access denied #01 10 Freescale factory access denied #10 11 Freescale factory access granted #11 KEYEN Backdoor Key Security Enable 6 2 read-only 00 Backdoor key access disabled #00 01 Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) #01 10 Backdoor key access enabled #10 11 Backdoor key access disabled #11 MEEN Mass Erase Enable 4 2 read-only 00 Mass erase is enabled #00 01 Mass erase is enabled #01 10 Mass erase is disabled #10 11 Mass erase is enabled #11 SEC Flash Security 0 2 read-only 00 MCU security status is secure. #00 01 MCU security status is secure. #01 10 MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.) #10 11 MCU security status is secure. #11 FSTAT Flash Status Register 0x0 8 read-write n 0x0 0x0 ACCERR Flash Access Error Flag 5 1 read-write 0 No access error detected #0 1 Access error detected #1 CCIF Command Complete Interrupt Flag 7 1 read-write 0 Flash command in progress #0 1 Flash command has completed #1 FPVIOL Flash Protection Violation Flag 4 1 read-write 0 No protection violation detected #0 1 Protection violation detected #1 MGSTAT0 Memory Controller Command Completion Status Flag 0 1 read-only RDCOLERR Flash Read Collision Error Flag 6 1 read-write 0 No collision error detected #0 1 Collision error detected #1 SACCH0 Supervisor-only Access Registers 0xA6 8 read-only n 0x0 0x0 SA Supervisor-only access control 0 8 read-only 0 Associated segment is accessible in supervisor mode only #0 1 Associated segment is accessible in user or supervisor mode #1 SACCH1 Supervisor-only Access Registers 0x83 8 read-only n 0x0 0x0 SA Supervisor-only access control 0 8 read-only 0 Associated segment is accessible in supervisor mode only #0 1 Associated segment is accessible in user or supervisor mode #1 SACCH2 Supervisor-only Access Registers 0x61 8 read-only n 0x0 0x0 SA Supervisor-only access control 0 8 read-only 0 Associated segment is accessible in supervisor mode only #0 1 Associated segment is accessible in user or supervisor mode #1 SACCH3 Supervisor-only Access Registers 0x40 8 read-only n 0x0 0x0 SA Supervisor-only access control 0 8 read-only 0 Associated segment is accessible in supervisor mode only #0 1 Associated segment is accessible in user or supervisor mode #1 SACCL0 Supervisor-only Access Registers 0x13C 8 read-only n 0x0 0x0 SA Supervisor-only access control 0 8 read-only 0 Associated segment is accessible in supervisor mode only #0 1 Associated segment is accessible in user or supervisor mode #1 SACCL1 Supervisor-only Access Registers 0x115 8 read-only n 0x0 0x0 SA Supervisor-only access control 0 8 read-only 0 Associated segment is accessible in supervisor mode only #0 1 Associated segment is accessible in user or supervisor mode #1 SACCL2 Supervisor-only Access Registers 0xEF 8 read-only n 0x0 0x0 SA Supervisor-only access control 0 8 read-only 0 Associated segment is accessible in supervisor mode only #0 1 Associated segment is accessible in user or supervisor mode #1 SACCL3 Supervisor-only Access Registers 0xCA 8 read-only n 0x0 0x0 SA Supervisor-only access control 0 8 read-only 0 Associated segment is accessible in supervisor mode only #0 1 Associated segment is accessible in user or supervisor mode #1 XACCH0 Execute-only Access Registers 0x7E 8 read-only n 0x0 0x0 XA Execute-only access control 0 8 read-only 0 Associated segment is accessible in execute mode only (as an instruction fetch) #0 1 Associated segment is accessible as data or in execute mode #1 XACCH1 Execute-only Access Registers 0x63 8 read-only n 0x0 0x0 XA Execute-only access control 0 8 read-only 0 Associated segment is accessible in execute mode only (as an instruction fetch) #0 1 Associated segment is accessible as data or in execute mode #1 XACCH2 Execute-only Access Registers 0x49 8 read-only n 0x0 0x0 XA Execute-only access control 0 8 read-only 0 Associated segment is accessible in execute mode only (as an instruction fetch) #0 1 Associated segment is accessible as data or in execute mode #1 XACCH3 Execute-only Access Registers 0x30 8 read-only n 0x0 0x0 XA Execute-only access control 0 8 read-only 0 Associated segment is accessible in execute mode only (as an instruction fetch) #0 1 Associated segment is accessible as data or in execute mode #1 XACCL0 Execute-only Access Registers 0xF4 8 read-only n 0x0 0x0 XA Execute-only access control 0 8 read-only 0 Associated segment is accessible in execute mode only (as an instruction fetch) #0 1 Associated segment is accessible as data or in execute mode #1 XACCL1 Execute-only Access Registers 0xD5 8 read-only n 0x0 0x0 XA Execute-only access control 0 8 read-only 0 Associated segment is accessible in execute mode only (as an instruction fetch) #0 1 Associated segment is accessible as data or in execute mode #1 XACCL2 Execute-only Access Registers 0xB7 8 read-only n 0x0 0x0 XA Execute-only access control 0 8 read-only 0 Associated segment is accessible in execute mode only (as an instruction fetch) #0 1 Associated segment is accessible as data or in execute mode #1 XACCL3 Execute-only Access Registers 0x9A 8 read-only n 0x0 0x0 XA Execute-only access control 0 8 read-only 0 Associated segment is accessible in execute mode only (as an instruction fetch) #0 1 Associated segment is accessible as data or in execute mode #1 FTFA_FlashConfig Flash configuration field FTFA_FlashConfig 0x0 0x0 0xE registers n NV_BACKKEY0 Backdoor Comparison Key 0. 0x3 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY1 Backdoor Comparison Key 1. 0x2 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY2 Backdoor Comparison Key 2. 0x1 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY3 Backdoor Comparison Key 3. 0x0 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY4 Backdoor Comparison Key 4. 0x7 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY5 Backdoor Comparison Key 5. 0x6 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY6 Backdoor Comparison Key 6. 0x5 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY7 Backdoor Comparison Key 7. 0x4 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_FOPT Non-volatile Flash Option Register 0xD 8 read-only n 0x0 0x0 BOOTPIN_OPT no description available 1 1 read-only 00 Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin #0 01 Boot source configured by FOPT (BOOTSRC_SEL) bits #1 BOOTSRC_SEL Boot source selection 6 2 read-only 00 Boot from Flash #00 10 Boot from ROM #10 11 Boot from ROM #11 FAST_INIT no description available 5 1 read-only 00 Slower initialization #0 01 Fast Initialization #1 LPBOOT0 no description available 0 1 read-only 00 Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1. #0 01 Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1. #1 LPBOOT1 no description available 4 1 read-only 00 Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1. #0 01 Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1. #1 NMI_DIS no description available 2 1 read-only 00 NMI interrupts are always blocked #0 01 NMI_b pin/interrupts reset default to enabled #1 RESET_PIN_CFG no description available 3 1 read-only 00 RESET pin is disabled following a POR and cannot be enabled as reset function #0 01 RESET_b pin is dedicated #1 NV_FPROT0 Non-volatile P-Flash Protection 0 - High Register 0xB 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only NV_FPROT1 Non-volatile P-Flash Protection 0 - Low Register 0xA 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only NV_FPROT2 Non-volatile P-Flash Protection 1 - High Register 0x9 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only NV_FPROT3 Non-volatile P-Flash Protection 1 - Low Register 0x8 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only NV_FSEC Non-volatile Flash Security Register 0xC 8 read-only n 0x0 0x0 FSLACC Freescale Failure Analysis Access Code 2 2 read-only 10 Freescale factory access denied #10 11 Freescale factory access granted #11 KEYEN Backdoor Key Security Enable 6 2 read-only 10 Backdoor key access enabled #10 11 Backdoor key access disabled #11 MEEN no description available 4 2 read-only 10 Mass erase is disabled #10 11 Mass erase is enabled #11 SEC Flash Security 0 2 read-only 10 MCU security status is unsecure #10 11 MCU security status is secure #11 GPIOA General Purpose Input/Output GPIO 0x0 0x0 0x18 registers n PORTA 17 PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 GPIOB General Purpose Input/Output GPIO 0x0 0x0 0x18 registers n PORTB 18 PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 GPIOC General Purpose Input/Output GPIO 0x0 0x0 0x18 registers n PORTC 19 PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 GPIOD General Purpose Input/Output GPIO 0x0 0x0 0x18 registers n PORTD 20 PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 GPIOE General Purpose Input/Output GPIO 0x0 0x0 0x18 registers n PORTE 21 PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 GPIOM General Purpose Input/Output GPIO 0x0 0x0 0x18 registers n PORTM 51 PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port Data Direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured as general-purpose output, for the GPIO function. #1 PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0, or is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 I2S0 Inter-IC Sound / Synchronous Audio Interface I2S0 0x0 0x0 0xE4 registers n I2S0 23 RCR1 SAI Receive Configuration 1 Register 0x84 32 read-write n 0x0 0x0 RFW Receive FIFO Watermark 0 2 read-write RCR2 SAI Receive Configuration 2 Register 0x88 32 read-write n 0x0 0x0 BCD Bit Clock Direction 24 1 read-write 0 Bit clock is generated externally in Slave mode. #0 1 Bit clock is generated internally in Master mode. #1 BCI Bit Clock Input 28 1 read-write 0 No effect. #0 1 Internal logic is clocked as if bit clock was externally generated. #1 BCP Bit Clock Polarity 25 1 read-write 0 Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. #0 1 Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. #1 BCS Bit Clock Swap 29 1 read-write 0 Use the normal bit clock source. #0 1 Swap the bit clock source. #1 DIV Bit Clock Divide 0 8 read-write MSEL MCLK Select 26 2 read-write 00 Bus Clock selected. #00 01 Master Clock (MCLK) 1 option selected. #01 10 Master Clock (MCLK) 2 option selected. #10 11 Master Clock (MCLK) 3 option selected. #11 SYNC Synchronous Mode 30 2 read-write 00 Asynchronous mode. #00 01 Synchronous with transmitter. #01 10 Synchronous with another SAI receiver. #10 11 Synchronous with another SAI transmitter. #11 RCR3 SAI Receive Configuration 3 Register 0x8C 32 read-write n 0x0 0x0 RCE Receive Channel Enable 16 1 read-write 0 Receive data channel N is disabled. #0 1 Receive data channel N is enabled. #1 WDFL Word Flag Configuration 0 4 read-write RCR4 SAI Receive Configuration 4 Register 0x90 32 read-write n 0x0 0x0 FCONT FIFO Continue on Error 28 1 read-write 0 On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. #0 1 On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. #1 FPACK FIFO Packing Mode 24 2 read-write 00 FIFO packing is disabled #00 10 8-bit FIFO packing is enabled #10 11 16-bit FIFO packing is enabled #11 FRSZ Frame Size 16 4 read-write FSD Frame Sync Direction 0 1 read-write 0 Frame Sync is generated externally in Slave mode. #0 1 Frame Sync is generated internally in Master mode. #1 FSE Frame Sync Early 3 1 read-write 0 Frame sync asserts with the first bit of the frame. #0 1 Frame sync asserts one bit before the first bit of the frame. #1 FSP Frame Sync Polarity 1 1 read-write 0 Frame sync is active high. #0 1 Frame sync is active low. #1 MF MSB First 4 1 read-write 0 LSB is received first. #0 1 MSB is received first. #1 ONDEM On Demand Mode 2 1 read-write 0 Internal frame sync is generated continuously. #0 1 Internal frame sync is generated when the FIFO warning flag is clear. #1 SYWD Sync Width 8 5 read-write RCR5 SAI Receive Configuration 5 Register 0x94 32 read-write n 0x0 0x0 FBT First Bit Shifted 8 5 read-write W0W Word 0 Width 16 5 read-write WNW Word N Width 24 5 read-write RCSR SAI Receive Control Register 0x80 32 read-write n 0x0 0x0 BCE Bit Clock Enable 28 1 read-write 0 Receive bit clock is disabled. #0 1 Receive bit clock is enabled. #1 DBGE Debug Enable 29 1 read-write 0 Receiver is disabled in Debug mode, after completing the current frame. #0 1 Receiver is enabled in Debug mode. #1 FEF FIFO Error Flag 18 1 read-write 0 Receive overflow not detected. #0 1 Receive overflow detected. #1 FEIE FIFO Error Interrupt Enable 10 1 read-write 0 Disables the interrupt. #0 1 Enables the interrupt. #1 FR FIFO Reset 25 1 write-only 0 No effect. #0 1 FIFO reset. #1 FRDE FIFO Request DMA Enable 0 1 read-write 0 Disables the DMA request. #0 1 Enables the DMA request. #1 FRF FIFO Request Flag 16 1 read-only 0 Receive FIFO watermark not reached. #0 1 Receive FIFO watermark has been reached. #1 FRIE FIFO Request Interrupt Enable 8 1 read-write 0 Disables the interrupt. #0 1 Enables the interrupt. #1 FWDE FIFO Warning DMA Enable 1 1 read-write 0 Disables the DMA request. #0 1 Enables the DMA request. #1 FWF FIFO Warning Flag 17 1 read-only 0 No enabled receive FIFO is full. #0 1 Enabled receive FIFO is full. #1 FWIE FIFO Warning Interrupt Enable 9 1 read-write 0 Disables the interrupt. #0 1 Enables the interrupt. #1 RE Receiver Enable 31 1 read-write 0 Receiver is disabled. #0 1 Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. #1 SEF Sync Error Flag 19 1 read-write 0 Sync error not detected. #0 1 Frame sync error detected. #1 SEIE Sync Error Interrupt Enable 11 1 read-write 0 Disables interrupt. #0 1 Enables interrupt. #1 SR Software Reset 24 1 read-write 0 No effect. #0 1 Software reset. #1 STOPE Stop Enable 30 1 read-write 0 Receiver disabled in Stop mode. #0 1 Receiver enabled in Stop mode. #1 WSF Word Start Flag 20 1 read-write 0 Start of word not detected. #0 1 Start of word detected. #1 WSIE Word Start Interrupt Enable 12 1 read-write 0 Disables interrupt. #0 1 Enables interrupt. #1 RDR SAI Receive Data Register 0xA0 32 read-only n 0x0 0x0 RDR Receive Data Register 0 32 read-only RFR SAI Receive FIFO Register 0xC0 32 read-only n 0x0 0x0 RFP Read FIFO Pointer 0 3 read-only WFP Write FIFO Pointer 16 3 read-only RMR SAI Receive Mask Register 0xE0 32 read-write n 0x0 0x0 RWM Receive Word Mask 0 16 read-write 0 Word N is enabled. #0 1 Word N is masked. #1 TCR1 SAI Transmit Configuration 1 Register 0x4 32 read-write n 0x0 0x0 TFW Transmit FIFO Watermark 0 2 read-write TCR2 SAI Transmit Configuration 2 Register 0x8 32 read-write n 0x0 0x0 BCD Bit Clock Direction 24 1 read-write 0 Bit clock is generated externally in Slave mode. #0 1 Bit clock is generated internally in Master mode. #1 BCI Bit Clock Input 28 1 read-write 0 No effect. #0 1 Internal logic is clocked as if bit clock was externally generated. #1 BCP Bit Clock Polarity 25 1 read-write 0 Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. #0 1 Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. #1 BCS Bit Clock Swap 29 1 read-write 0 Use the normal bit clock source. #0 1 Swap the bit clock source. #1 DIV Bit Clock Divide 0 8 read-write MSEL MCLK Select 26 2 read-write 01 Master Clock (MCLK) 1 option selected. #01 10 Master Clock (MCLK) 2 option selected. #10 11 Master Clock (MCLK) 3 option selected. #11 SYNC Synchronous Mode 30 2 read-write 00 Asynchronous mode. #00 01 Synchronous with receiver. #01 10 Synchronous with another SAI transmitter. #10 11 Synchronous with another SAI receiver. #11 TCR3 SAI Transmit Configuration 3 Register 0xC 32 read-write n 0x0 0x0 TCE Transmit Channel Enable 16 1 read-write 0 Transmit data channel N is disabled. #0 1 Transmit data channel N is enabled. #1 WDFL Word Flag Configuration 0 4 read-write TCR4 SAI Transmit Configuration 4 Register 0x10 32 read-write n 0x0 0x0 FCONT FIFO Continue on Error 28 1 read-write 0 On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. #0 1 On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. #1 FPACK FIFO Packing Mode 24 2 read-write 00 FIFO packing is disabled #00 10 8-bit FIFO packing is enabled #10 11 16-bit FIFO packing is enabled #11 FRSZ Frame size 16 4 read-write FSD Frame Sync Direction 0 1 read-write 0 Frame sync is generated externally in Slave mode. #0 1 Frame sync is generated internally in Master mode. #1 FSE Frame Sync Early 3 1 read-write 0 Frame sync asserts with the first bit of the frame. #0 1 Frame sync asserts one bit before the first bit of the frame. #1 FSP Frame Sync Polarity 1 1 read-write 0 Frame sync is active high. #0 1 Frame sync is active low. #1 MF MSB First 4 1 read-write 0 LSB is transmitted first. #0 1 MSB is transmitted first. #1 ONDEM On Demand Mode 2 1 read-write 0 Internal frame sync is generated continuously. #0 1 Internal frame sync is generated when the FIFO warning flag is clear. #1 SYWD Sync Width 8 5 read-write TCR5 SAI Transmit Configuration 5 Register 0x14 32 read-write n 0x0 0x0 FBT First Bit Shifted 8 5 read-write W0W Word 0 Width 16 5 read-write WNW Word N Width 24 5 read-write TCSR SAI Transmit Control Register 0x0 32 read-write n 0x0 0x0 BCE Bit Clock Enable 28 1 read-write 0 Transmit bit clock is disabled. #0 1 Transmit bit clock is enabled. #1 DBGE Debug Enable 29 1 read-write 0 Transmitter is disabled in Debug mode, after completing the current frame. #0 1 Transmitter is enabled in Debug mode. #1 FEF FIFO Error Flag 18 1 read-write 0 Transmit underrun not detected. #0 1 Transmit underrun detected. #1 FEIE FIFO Error Interrupt Enable 10 1 read-write 0 Disables the interrupt. #0 1 Enables the interrupt. #1 FR FIFO Reset 25 1 write-only 0 No effect. #0 1 FIFO reset. #1 FRDE FIFO Request DMA Enable 0 1 read-write 0 Disables the DMA request. #0 1 Enables the DMA request. #1 FRF FIFO Request Flag 16 1 read-only 0 Transmit FIFO watermark has not been reached. #0 1 Transmit FIFO watermark has been reached. #1 FRIE FIFO Request Interrupt Enable 8 1 read-write 0 Disables the interrupt. #0 1 Enables the interrupt. #1 FWDE FIFO Warning DMA Enable 1 1 read-write 0 Disables the DMA request. #0 1 Enables the DMA request. #1 FWF FIFO Warning Flag 17 1 read-only 0 No enabled transmit FIFO is empty. #0 1 Enabled transmit FIFO is empty. #1 FWIE FIFO Warning Interrupt Enable 9 1 read-write 0 Disables the interrupt. #0 1 Enables the interrupt. #1 SEF Sync Error Flag 19 1 read-write 0 Sync error not detected. #0 1 Frame sync error detected. #1 SEIE Sync Error Interrupt Enable 11 1 read-write 0 Disables interrupt. #0 1 Enables interrupt. #1 SR Software Reset 24 1 read-write 0 No effect. #0 1 Software reset. #1 STOPE Stop Enable 30 1 read-write 0 Transmitter disabled in Stop mode. #0 1 Transmitter enabled in Stop mode. #1 TE Transmitter Enable 31 1 read-write 0 Transmitter is disabled. #0 1 Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. #1 WSF Word Start Flag 20 1 read-write 0 Start of word not detected. #0 1 Start of word detected. #1 WSIE Word Start Interrupt Enable 12 1 read-write 0 Disables interrupt. #0 1 Enables interrupt. #1 TDR SAI Transmit Data Register 0x20 32 write-only n 0x0 0x0 TDR Transmit Data Register 0 32 write-only TFR SAI Transmit FIFO Register 0x40 32 read-only n 0x0 0x0 RFP Read FIFO Pointer 0 3 read-only WFP Write FIFO Pointer 16 3 read-only TMR SAI Transmit Mask Register 0x60 32 read-write n 0x0 0x0 TWM Transmit Word Mask 0 16 read-write 0 Word N is enabled. #0 1 Word N is masked. The transmit data pins are tri-stated when masked. #1 INTMUX0 Interrupt Multiplexer INTMUX0 0x0 0x0 0xE4 registers n INTMUX0_0 28 INTMUX0_1 29 INTMUX0_2 30 INTMUX0_3 31 CH0_CSR Channel n Control Status Register 0x0 32 read-write n 0x0 0x0 AND Logic AND 1 1 read-write 0 Logic OR all enabled interrupt inputs. #0 1 Logic AND all enabled interrupt inputs. #1 CHIN Channel Instance Number 8 4 read-only IRQN Channel Input Number 4 2 read-only 00 32 interrupt inputs #00 IRQP Channel Interrupt Request Pending 31 1 read-only 0 No interrupt is pending. #0 1 The interrupt output of this channel is pending. #1 RST Software Reset 0 1 read-write 0 No operation. #0 1 Perform a software reset on this channel. #1 CH0_IER_31_0 Channel n Interrupt Enable Register 0x20 32 read-write n 0x0 0x0 INTE Interrupt Enable 0 32 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 CH0_IPR_31_0 Channel n Interrupt Pending Register 0x40 32 read-only n 0x0 0x0 INTP Interrupt Pending 0 32 read-only 0 No interrupt. #0 1 Interrupt is pending. #1 CH0_VEC Channel n Vector Number Register 0x8 32 read-only n 0x0 0x0 VECN Vector Number 2 12 read-only CH1_CSR Channel n Control Status Register 0x40 32 read-write n 0x0 0x0 AND Logic AND 1 1 read-write 0 Logic OR all enabled interrupt inputs. #0 1 Logic AND all enabled interrupt inputs. #1 CHIN Channel Instance Number 8 4 read-only IRQN Channel Input Number 4 2 read-only 00 32 interrupt inputs #00 IRQP Channel Interrupt Request Pending 31 1 read-only 0 No interrupt is pending. #0 1 The interrupt output of this channel is pending. #1 RST Software Reset 0 1 read-write 0 No operation. #0 1 Perform a software reset on this channel. #1 CH1_IER_31_0 Channel n Interrupt Enable Register 0x70 32 read-write n 0x0 0x0 INTE Interrupt Enable 0 32 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 CH1_IPR_31_0 Channel n Interrupt Pending Register 0xA0 32 read-only n 0x0 0x0 INTP Interrupt Pending 0 32 read-only 0 No interrupt. #0 1 Interrupt is pending. #1 CH1_VEC Channel n Vector Number Register 0x4C 32 read-only n 0x0 0x0 VECN Vector Number 2 12 read-only CH2_CSR Channel n Control Status Register 0xC0 32 read-write n 0x0 0x0 AND Logic AND 1 1 read-write 0 Logic OR all enabled interrupt inputs. #0 1 Logic AND all enabled interrupt inputs. #1 CHIN Channel Instance Number 8 4 read-only IRQN Channel Input Number 4 2 read-only 00 32 interrupt inputs #00 IRQP Channel Interrupt Request Pending 31 1 read-only 0 No interrupt is pending. #0 1 The interrupt output of this channel is pending. #1 RST Software Reset 0 1 read-write 0 No operation. #0 1 Perform a software reset on this channel. #1 CH2_IER_31_0 Channel n Interrupt Enable Register 0x100 32 read-write n 0x0 0x0 INTE Interrupt Enable 0 32 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 CH2_IPR_31_0 Channel n Interrupt Pending Register 0x140 32 read-only n 0x0 0x0 INTP Interrupt Pending 0 32 read-only 0 No interrupt. #0 1 Interrupt is pending. #1 CH2_VEC Channel n Vector Number Register 0xD0 32 read-only n 0x0 0x0 VECN Vector Number 2 12 read-only CH3_CSR Channel n Control Status Register 0x180 32 read-write n 0x0 0x0 AND Logic AND 1 1 read-write 0 Logic OR all enabled interrupt inputs. #0 1 Logic AND all enabled interrupt inputs. #1 CHIN Channel Instance Number 8 4 read-only IRQN Channel Input Number 4 2 read-only 00 32 interrupt inputs #00 IRQP Channel Interrupt Request Pending 31 1 read-only 0 No interrupt is pending. #0 1 The interrupt output of this channel is pending. #1 RST Software Reset 0 1 read-write 0 No operation. #0 1 Perform a software reset on this channel. #1 CH3_IER_31_0 Channel n Interrupt Enable Register 0x1D0 32 read-write n 0x0 0x0 INTE Interrupt Enable 0 32 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 CH3_IPR_31_0 Channel n Interrupt Pending Register 0x220 32 read-only n 0x0 0x0 INTP Interrupt Pending 0 32 read-only 0 No interrupt. #0 1 Interrupt is pending. #1 CH3_VEC Channel n Vector Number Register 0x194 32 read-only n 0x0 0x0 VECN Vector Number 2 12 read-only LLWU0 Low leakage wakeup unit LLWU 0x0 0x0 0x30 registers n LLWU0 22 DE LLWU Module DMA Enable register 0x1C 32 read-write n 0x0 0x0 WUDE0 DMA Wakeup Enable For Module 0 0 1 read-write 0 Internal module request not used as a DMA wakeup source #0 1 Internal module request used as a DMA wakeup source #1 WUDE1 DMA Wakeup Enable for Module 1 1 1 read-write 0 Internal module request not used as a DMA wakeup source #0 1 Internal module request used as a DMA wakeup source #1 WUDE2 DMA Wakeup Enable For Module 2 2 1 read-write 0 Internal module request not used as a DMA wakeup source #0 1 Internal module request used as a DMA wakeup source #1 WUDE3 DMA Wakeup Enable For Module 3 3 1 read-write 0 Internal module request not used as a DMA wakeup source #0 1 Internal module request used as a DMA wakeup source #1 WUDE4 DMA Wakeup Enable For Module 4 4 1 read-write 0 Internal module request not used as a DMA wakeup source #0 1 Internal module request used as a DMA wakeup source #1 WUDE5 DMA Wakeup Enable For Module 5 5 1 read-write 0 Internal module request not used as a DMA wakeup source #0 1 Internal module request used as a DMA wakeup source #1 WUDE6 DMA Wakeup Enable For Module 6 6 1 read-write 0 Internal module request not used as a DMA wakeup source #0 1 Internal module request used as a DMA wakeup source #1 WUDE7 DMA Wakeup Enable For Module 7 7 1 read-write 0 Internal module request not used as a DMA wakeup source #0 1 Internal module request used as a DMA wakeup source #1 FILT LLWU Pin Filter register 0x30 32 read-write n 0x0 0x0 FILTE1 Filter 1 Enable 5 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTE2 Filter 2 Enable 13 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTE3 Filter 3 Enable 21 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTE4 Filter 4 Enable 29 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTF1 Filter 1 Flag 7 1 read-write 0 Pin Filter 1 was not a wakeup source #0 1 Pin Filter 1 was a wakeup source #1 FILTF2 Filter 2 Flag 15 1 read-write 0 Pin Filter 1 was not a wakeup source #0 1 Pin Filter 1 was a wakeup source #1 FILTF3 Filter 3 Flag 23 1 read-write 0 Pin Filter 1 was not a wakeup source #0 1 Pin Filter 1 was a wakeup source #1 FILTF4 Filter 4 Flag 31 1 read-write 0 Pin Filter 1 was not a wakeup source #0 1 Pin Filter 1 was a wakeup source #1 FILTSEL1 Filter 1 Pin Select 0 5 read-write 00000 Select LLWU_P0 for filter #00000 11111 Select LLWU_P31 for filter #11111 FILTSEL2 Filter 2 Pin Select 8 5 read-write 00000 Select LLWU_P0 for filter #00000 11111 Select LLWU_P31 for filter #11111 FILTSEL3 Filter 3 Pin Select 16 5 read-write 00000 Select LLWU_P0 for filter #00000 11111 Select LLWU_P31 for filter #11111 FILTSEL4 Filter 4 Pin Select 24 5 read-write 00000 Select LLWU_P0 for filter #00000 11111 Select LLWU_P31 for filter #11111 ME LLWU Module Interrupt Enable register 0x18 32 read-write n 0x0 0x0 WUME0 Wakeup Module Enable For Module 0 0 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME1 Wakeup Module Enable for Module 1 1 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME2 Wakeup Module Enable For Module 2 2 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME3 Wakeup Module Enable For Module 3 3 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME4 Wakeup Module Enable For Module 4 4 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME5 Wakeup Module Enable For Module 5 5 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME6 Wakeup Module Enable For Module 6 6 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME7 Wakeup Module Enable For Module 7 7 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 MF LLWU Module Interrupt Flag register 0x28 32 read-only n 0x0 0x0 MWUF0 Wakeup flag For module 0 0 1 read-only 0 Module 0 input was not a wakeup source #0 1 Module 0 input was a wakeup source #1 MWUF1 Wakeup flag For module 1 1 1 read-only 0 Module 1 input was not a wakeup source #0 1 Module 1 input was a wakeup source #1 MWUF2 Wakeup flag For module 2 2 1 read-only 0 Module 2 input was not a wakeup source #0 1 Module 2 input was a wakeup source #1 MWUF3 Wakeup flag For module 3 3 1 read-only 0 Module 3 input was not a wakeup source #0 1 Module 3 input was a wakeup source #1 MWUF4 Wakeup flag For module 4 4 1 read-only 0 Module 4 input was not a wakeup source #0 1 Module 4 input was a wakeup source #1 MWUF5 Wakeup flag For module 5 5 1 read-only 0 Module 5 input was not a wakeup source #0 1 Module 5 input was a wakeup source #1 MWUF6 Wakeup flag For module 6 6 1 read-only 0 Module 6 input was not a wakeup source #0 1 Module 6 input was a wakeup source #1 MWUF7 Wakeup flag For module 7 7 1 read-only 0 Module 7 input was not a wakeup source #0 1 Module 7 input was a wakeup source #1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 DMAS DMA Number 8 8 read-only FILTERS Filter Number 0 8 read-only MODULES Module Number 16 8 read-only PINS Pin Number 24 8 read-only PE1 LLWU Pin Enable 1 register 0x8 32 read-write n 0x0 0x0 WUPE0 Wakeup Pin Enable For LLWU_P0 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE1 Wakeup Pin Enable For LLWU_P1 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE10 Wakeup Pin Enable For LLWU_P10 20 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE11 Wakeup Pin Enable For LLWU_P11 22 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE12 Wakeup Pin Enable For LLWU_P12 24 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE13 Wakeup Pin Enable For LLWU_P13 26 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE14 Wakeup Pin Enable For LLWU_P14 28 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE15 Wakeup Pin Enable For LLWU_P15 30 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE2 Wakeup Pin Enable For LLWU_P2 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE3 Wakeup Pin Enable For LLWU_P3 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE4 Wakeup Pin Enable For LLWU_P4 8 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE5 Wakeup Pin Enable For LLWU_P5 10 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE6 Wakeup Pin Enable For LLWU_P6 12 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE7 Wakeup Pin Enable For LLWU_P7 14 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE8 Wakeup Pin Enable For LLWU_P8 16 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE9 Wakeup Pin Enable For LLWU_P9 18 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE2 LLWU Pin Enable 2 register 0xC 32 read-write n 0x0 0x0 WUPE16 Wakeup Pin Enable For LLWU_P16 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE17 Wakeup Pin Enable For LLWU_P17 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE18 Wakeup Pin Enable For LLWU_P18 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE19 Wakeup Pin Enable For LLWU_P19 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE20 Wakeup Pin Enable For LLWU_P20 8 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE21 Wakeup Pin Enable For LLWU_P21 10 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE22 Wakeup Pin Enable For LLWU_P22 12 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE23 Wakeup Pin Enable For LLWU_P23 14 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE24 Wakeup Pin Enable For LLWU_P24 16 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE25 Wakeup Pin Enable For LLWU_P25 18 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE26 Wakeup Pin Enable For LLWU_P26 20 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE27 Wakeup Pin Enable For LLWU_P27 22 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE28 Wakeup Pin Enable For LLWU_P28 24 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE29 Wakeup Pin Enable For LLWU_P29 26 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE30 Wakeup Pin Enable For LLWU_P30 28 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE31 Wakeup Pin Enable For LLWU_P31 30 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PF LLWU Pin Flag register 0x20 32 read-write n 0x0 0x0 WUF0 Wakeup Flag For LLWU_P0 0 1 read-write 0 LLWU_P0 input was not a wakeup source #0 1 LLWU_P0 input was a wakeup source #1 WUF1 Wakeup Flag For LLWU_P1 1 1 read-write 0 LLWU_P1 input was not a wakeup source #0 1 LLWU_P1 input was a wakeup source #1 WUF10 Wakeup Flag For LLWU_P10 10 1 read-write 0 LLWU_P10 input was not a wakeup source #0 1 LLWU_P10 input was a wakeup source #1 WUF11 Wakeup Flag For LLWU_P11 11 1 read-write 0 LLWU_P11 input was not a wakeup source #0 1 LLWU_P11 input was a wakeup source #1 WUF12 Wakeup Flag For LLWU_P12 12 1 read-write 0 LLWU_P12 input was not a wakeup source #0 1 LLWU_P12 input was a wakeup source #1 WUF13 Wakeup Flag For LLWU_P13 13 1 read-write 0 LLWU_P13 input was not a wakeup source #0 1 LLWU_P13 input was a wakeup source #1 WUF14 Wakeup Flag For LLWU_P14 14 1 read-write 0 LLWU_P14 input was not a wakeup source #0 1 LLWU_P14 input was a wakeup source #1 WUF15 Wakeup Flag For LLWU_P15 15 1 read-write 0 LLWU_P15 input was not a wakeup source #0 1 LLWU_P15 input was a wakeup source #1 WUF16 Wakeup Flag For LLWU_P16 16 1 read-write 0 LLWU_P16 input was not a wakeup source #0 1 LLWU_P16 input was a wakeup source #1 WUF17 Wakeup Flag For LLWU_P17 17 1 read-write 0 LLWU_P17 input was not a wakeup source #0 1 LLWU_P17 input was a wakeup source #1 WUF18 Wakeup Flag For LLWU_P18 18 1 read-write 0 LLWU_P18 input was not a wakeup source #0 1 LLWU_P18 input was a wakeup source #1 WUF19 Wakeup Flag For LLWU_P19 19 1 read-write 0 LLWU_P19 input was not a wakeup source #0 1 LLWU_P19 input was a wakeup source #1 WUF2 Wakeup Flag For LLWU_P2 2 1 read-write 0 LLWU_P2 input was not a wakeup source #0 1 LLWU_P2 input was a wakeup source #1 WUF20 Wakeup Flag For LLWU_P20 20 1 read-write 0 LLWU_P20 input was not a wakeup source #0 1 LLWU_P20 input was a wakeup source #1 WUF21 Wakeup Flag For LLWU_P21 21 1 read-write 0 LLWU_P21 input was not a wakeup source #0 1 LLWU_P21 input was a wakeup source #1 WUF22 Wakeup Flag For LLWU_P22 22 1 read-write 0 LLWU_P22 input was not a wakeup source #0 1 LLWU_P22 input was a wakeup source #1 WUF23 Wakeup Flag For LLWU_P23 23 1 read-write 0 LLWU_P23 input was not a wakeup source #0 1 LLWU_P23 input was a wakeup source #1 WUF24 Wakeup Flag For LLWU_P24 24 1 read-write 0 LLWU_P24 input was not a wakeup source #0 1 LLWU_P24 input was a wakeup source #1 WUF25 Wakeup Flag For LLWU_P25 25 1 read-write 0 LLWU_P25 input was not a wakeup source #0 1 LLWU_P25 input was a wakeup source #1 WUF26 Wakeup Flag For LLWU_P26 26 1 read-write 0 LLWU_P26 input was not a wakeup source #0 1 LLWU_P26 input was a wakeup source #1 WUF27 Wakeup Flag For LLWU_P27 27 1 read-write 0 LLWU_P27 input was not a wakeup source #0 1 LLWU_P27 input was a wakeup source #1 WUF28 Wakeup Flag For LLWU_P28 28 1 read-write 0 LLWU_P28 input was not a wakeup source #0 1 LLWU_P28 input was a wakeup source #1 WUF29 Wakeup Flag For LLWU_P29 29 1 read-write 0 LLWU_P29 input was not a wakeup source #0 1 LLWU_P29 input was a wakeup source #1 WUF3 Wakeup Flag For LLWU_P3 3 1 read-write 0 LLWU_P3 input was not a wakeup source #0 1 LLWU_P3 input was a wakeup source #1 WUF30 Wakeup Flag For LLWU_P30 30 1 read-write 0 LLWU_P30 input was not a wakeup source #0 1 LLWU_P30 input was a wakeup source #1 WUF31 Wakeup Flag For LLWU_P31 31 1 read-write 0 LLWU_P31 input was not a wakeup source #0 1 LLWU_P31 input was a wakeup source #1 WUF4 Wakeup Flag For LLWU_P4 4 1 read-write 0 LLWU_P4 input was not a wakeup source #0 1 LLWU_P4 input was a wakeup source #1 WUF5 Wakeup Flag For LLWU_P5 5 1 read-write 0 LLWU_P5 input was not a wakeup source #0 1 LLWU_P5 input was a wakeup source #1 WUF6 Wakeup Flag For LLWU_P6 6 1 read-write 0 LLWU_P6 input was not a wakeup source #0 1 LLWU_P6 input was a wakeup source #1 WUF7 Wakeup Flag For LLWU_P7 7 1 read-write 0 LLWU_P7 input was not a wakeup source #0 1 LLWU_P7 input was a wakeup source #1 WUF8 Wakeup Flag For LLWU_P8 8 1 read-write 0 LLWU_P8 input was not a wakeup source #0 1 LLWU_P8 input was a wakeup source #1 WUF9 Wakeup Flag For LLWU_P9 9 1 read-write 0 LLWU_P9 input was not a wakeup source #0 1 LLWU_P9 input was a wakeup source #1 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Specification Number 0 16 read-only 0 Standard features implemented #0 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only LLWU1 Low leakage wakeup unit LLWU 0x0 0x0 0x30 registers n DE LLWU Module DMA Enable register 0x1C 32 read-write n 0x0 0x0 WUDE0 DMA Wakeup Enable For Module 0 0 1 read-write 0 Internal module request not used as a DMA wakeup source #0 1 Internal module request used as a DMA wakeup source #1 WUDE1 DMA Wakeup Enable for Module 1 1 1 read-write 0 Internal module request not used as a DMA wakeup source #0 1 Internal module request used as a DMA wakeup source #1 WUDE2 DMA Wakeup Enable For Module 2 2 1 read-write 0 Internal module request not used as a DMA wakeup source #0 1 Internal module request used as a DMA wakeup source #1 WUDE3 DMA Wakeup Enable For Module 3 3 1 read-write 0 Internal module request not used as a DMA wakeup source #0 1 Internal module request used as a DMA wakeup source #1 WUDE4 DMA Wakeup Enable For Module 4 4 1 read-write 0 Internal module request not used as a DMA wakeup source #0 1 Internal module request used as a DMA wakeup source #1 WUDE5 DMA Wakeup Enable For Module 5 5 1 read-write 0 Internal module request not used as a DMA wakeup source #0 1 Internal module request used as a DMA wakeup source #1 WUDE6 DMA Wakeup Enable For Module 6 6 1 read-write 0 Internal module request not used as a DMA wakeup source #0 1 Internal module request used as a DMA wakeup source #1 WUDE7 DMA Wakeup Enable For Module 7 7 1 read-write 0 Internal module request not used as a DMA wakeup source #0 1 Internal module request used as a DMA wakeup source #1 FILT LLWU Pin Filter register 0x30 32 read-write n 0x0 0x0 FILTE1 Filter 1 Enable 5 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTE2 Filter 2 Enable 13 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTE3 Filter 3 Enable 21 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTE4 Filter 4 Enable 29 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTF1 Filter 1 Flag 7 1 read-write 0 Pin Filter 1 was not a wakeup source #0 1 Pin Filter 1 was a wakeup source #1 FILTF2 Filter 2 Flag 15 1 read-write 0 Pin Filter 1 was not a wakeup source #0 1 Pin Filter 1 was a wakeup source #1 FILTF3 Filter 3 Flag 23 1 read-write 0 Pin Filter 1 was not a wakeup source #0 1 Pin Filter 1 was a wakeup source #1 FILTF4 Filter 4 Flag 31 1 read-write 0 Pin Filter 1 was not a wakeup source #0 1 Pin Filter 1 was a wakeup source #1 FILTSEL1 Filter 1 Pin Select 0 5 read-write 00000 Select LLWU_P0 for filter #00000 11111 Select LLWU_P31 for filter #11111 FILTSEL2 Filter 2 Pin Select 8 5 read-write 00000 Select LLWU_P0 for filter #00000 11111 Select LLWU_P31 for filter #11111 FILTSEL3 Filter 3 Pin Select 16 5 read-write 00000 Select LLWU_P0 for filter #00000 11111 Select LLWU_P31 for filter #11111 FILTSEL4 Filter 4 Pin Select 24 5 read-write 00000 Select LLWU_P0 for filter #00000 11111 Select LLWU_P31 for filter #11111 ME LLWU Module Interrupt Enable register 0x18 32 read-write n 0x0 0x0 WUME0 Wakeup Module Enable For Module 0 0 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME1 Wakeup Module Enable for Module 1 1 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME2 Wakeup Module Enable For Module 2 2 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME3 Wakeup Module Enable For Module 3 3 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME4 Wakeup Module Enable For Module 4 4 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME5 Wakeup Module Enable For Module 5 5 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME6 Wakeup Module Enable For Module 6 6 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME7 Wakeup Module Enable For Module 7 7 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 MF LLWU Module Interrupt Flag register 0x28 32 read-only n 0x0 0x0 MWUF0 Wakeup flag For module 0 0 1 read-only 0 Module 0 input was not a wakeup source #0 1 Module 0 input was a wakeup source #1 MWUF1 Wakeup flag For module 1 1 1 read-only 0 Module 1 input was not a wakeup source #0 1 Module 1 input was a wakeup source #1 MWUF2 Wakeup flag For module 2 2 1 read-only 0 Module 2 input was not a wakeup source #0 1 Module 2 input was a wakeup source #1 MWUF3 Wakeup flag For module 3 3 1 read-only 0 Module 3 input was not a wakeup source #0 1 Module 3 input was a wakeup source #1 MWUF4 Wakeup flag For module 4 4 1 read-only 0 Module 4 input was not a wakeup source #0 1 Module 4 input was a wakeup source #1 MWUF5 Wakeup flag For module 5 5 1 read-only 0 Module 5 input was not a wakeup source #0 1 Module 5 input was a wakeup source #1 MWUF6 Wakeup flag For module 6 6 1 read-only 0 Module 6 input was not a wakeup source #0 1 Module 6 input was a wakeup source #1 MWUF7 Wakeup flag For module 7 7 1 read-only 0 Module 7 input was not a wakeup source #0 1 Module 7 input was a wakeup source #1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 DMAS DMA Number 8 8 read-only FILTERS Filter Number 0 8 read-only MODULES Module Number 16 8 read-only PINS Pin Number 24 8 read-only PE1 LLWU Pin Enable 1 register 0x8 32 read-write n 0x0 0x0 WUPE0 Wakeup Pin Enable For LLWU_P0 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE1 Wakeup Pin Enable For LLWU_P1 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE10 Wakeup Pin Enable For LLWU_P10 20 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE11 Wakeup Pin Enable For LLWU_P11 22 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE12 Wakeup Pin Enable For LLWU_P12 24 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE13 Wakeup Pin Enable For LLWU_P13 26 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE14 Wakeup Pin Enable For LLWU_P14 28 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE15 Wakeup Pin Enable For LLWU_P15 30 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE2 Wakeup Pin Enable For LLWU_P2 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE3 Wakeup Pin Enable For LLWU_P3 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE4 Wakeup Pin Enable For LLWU_P4 8 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE5 Wakeup Pin Enable For LLWU_P5 10 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE6 Wakeup Pin Enable For LLWU_P6 12 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE7 Wakeup Pin Enable For LLWU_P7 14 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE8 Wakeup Pin Enable For LLWU_P8 16 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE9 Wakeup Pin Enable For LLWU_P9 18 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE2 LLWU Pin Enable 2 register 0xC 32 read-write n 0x0 0x0 WUPE16 Wakeup Pin Enable For LLWU_P16 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE17 Wakeup Pin Enable For LLWU_P17 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE18 Wakeup Pin Enable For LLWU_P18 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE19 Wakeup Pin Enable For LLWU_P19 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE20 Wakeup Pin Enable For LLWU_P20 8 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE21 Wakeup Pin Enable For LLWU_P21 10 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE22 Wakeup Pin Enable For LLWU_P22 12 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE23 Wakeup Pin Enable For LLWU_P23 14 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE24 Wakeup Pin Enable For LLWU_P24 16 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE25 Wakeup Pin Enable For LLWU_P25 18 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE26 Wakeup Pin Enable For LLWU_P26 20 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE27 Wakeup Pin Enable For LLWU_P27 22 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE28 Wakeup Pin Enable For LLWU_P28 24 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE29 Wakeup Pin Enable For LLWU_P29 26 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE30 Wakeup Pin Enable For LLWU_P30 28 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE31 Wakeup Pin Enable For LLWU_P31 30 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PF LLWU Pin Flag register 0x20 32 read-write n 0x0 0x0 WUF0 Wakeup Flag For LLWU_P0 0 1 read-write 0 LLWU_P0 input was not a wakeup source #0 1 LLWU_P0 input was a wakeup source #1 WUF1 Wakeup Flag For LLWU_P1 1 1 read-write 0 LLWU_P1 input was not a wakeup source #0 1 LLWU_P1 input was a wakeup source #1 WUF10 Wakeup Flag For LLWU_P10 10 1 read-write 0 LLWU_P10 input was not a wakeup source #0 1 LLWU_P10 input was a wakeup source #1 WUF11 Wakeup Flag For LLWU_P11 11 1 read-write 0 LLWU_P11 input was not a wakeup source #0 1 LLWU_P11 input was a wakeup source #1 WUF12 Wakeup Flag For LLWU_P12 12 1 read-write 0 LLWU_P12 input was not a wakeup source #0 1 LLWU_P12 input was a wakeup source #1 WUF13 Wakeup Flag For LLWU_P13 13 1 read-write 0 LLWU_P13 input was not a wakeup source #0 1 LLWU_P13 input was a wakeup source #1 WUF14 Wakeup Flag For LLWU_P14 14 1 read-write 0 LLWU_P14 input was not a wakeup source #0 1 LLWU_P14 input was a wakeup source #1 WUF15 Wakeup Flag For LLWU_P15 15 1 read-write 0 LLWU_P15 input was not a wakeup source #0 1 LLWU_P15 input was a wakeup source #1 WUF16 Wakeup Flag For LLWU_P16 16 1 read-write 0 LLWU_P16 input was not a wakeup source #0 1 LLWU_P16 input was a wakeup source #1 WUF17 Wakeup Flag For LLWU_P17 17 1 read-write 0 LLWU_P17 input was not a wakeup source #0 1 LLWU_P17 input was a wakeup source #1 WUF18 Wakeup Flag For LLWU_P18 18 1 read-write 0 LLWU_P18 input was not a wakeup source #0 1 LLWU_P18 input was a wakeup source #1 WUF19 Wakeup Flag For LLWU_P19 19 1 read-write 0 LLWU_P19 input was not a wakeup source #0 1 LLWU_P19 input was a wakeup source #1 WUF2 Wakeup Flag For LLWU_P2 2 1 read-write 0 LLWU_P2 input was not a wakeup source #0 1 LLWU_P2 input was a wakeup source #1 WUF20 Wakeup Flag For LLWU_P20 20 1 read-write 0 LLWU_P20 input was not a wakeup source #0 1 LLWU_P20 input was a wakeup source #1 WUF21 Wakeup Flag For LLWU_P21 21 1 read-write 0 LLWU_P21 input was not a wakeup source #0 1 LLWU_P21 input was a wakeup source #1 WUF22 Wakeup Flag For LLWU_P22 22 1 read-write 0 LLWU_P22 input was not a wakeup source #0 1 LLWU_P22 input was a wakeup source #1 WUF23 Wakeup Flag For LLWU_P23 23 1 read-write 0 LLWU_P23 input was not a wakeup source #0 1 LLWU_P23 input was a wakeup source #1 WUF24 Wakeup Flag For LLWU_P24 24 1 read-write 0 LLWU_P24 input was not a wakeup source #0 1 LLWU_P24 input was a wakeup source #1 WUF25 Wakeup Flag For LLWU_P25 25 1 read-write 0 LLWU_P25 input was not a wakeup source #0 1 LLWU_P25 input was a wakeup source #1 WUF26 Wakeup Flag For LLWU_P26 26 1 read-write 0 LLWU_P26 input was not a wakeup source #0 1 LLWU_P26 input was a wakeup source #1 WUF27 Wakeup Flag For LLWU_P27 27 1 read-write 0 LLWU_P27 input was not a wakeup source #0 1 LLWU_P27 input was a wakeup source #1 WUF28 Wakeup Flag For LLWU_P28 28 1 read-write 0 LLWU_P28 input was not a wakeup source #0 1 LLWU_P28 input was a wakeup source #1 WUF29 Wakeup Flag For LLWU_P29 29 1 read-write 0 LLWU_P29 input was not a wakeup source #0 1 LLWU_P29 input was a wakeup source #1 WUF3 Wakeup Flag For LLWU_P3 3 1 read-write 0 LLWU_P3 input was not a wakeup source #0 1 LLWU_P3 input was a wakeup source #1 WUF30 Wakeup Flag For LLWU_P30 30 1 read-write 0 LLWU_P30 input was not a wakeup source #0 1 LLWU_P30 input was a wakeup source #1 WUF31 Wakeup Flag For LLWU_P31 31 1 read-write 0 LLWU_P31 input was not a wakeup source #0 1 LLWU_P31 input was a wakeup source #1 WUF4 Wakeup Flag For LLWU_P4 4 1 read-write 0 LLWU_P4 input was not a wakeup source #0 1 LLWU_P4 input was a wakeup source #1 WUF5 Wakeup Flag For LLWU_P5 5 1 read-write 0 LLWU_P5 input was not a wakeup source #0 1 LLWU_P5 input was a wakeup source #1 WUF6 Wakeup Flag For LLWU_P6 6 1 read-write 0 LLWU_P6 input was not a wakeup source #0 1 LLWU_P6 input was a wakeup source #1 WUF7 Wakeup Flag For LLWU_P7 7 1 read-write 0 LLWU_P7 input was not a wakeup source #0 1 LLWU_P7 input was a wakeup source #1 WUF8 Wakeup Flag For LLWU_P8 8 1 read-write 0 LLWU_P8 input was not a wakeup source #0 1 LLWU_P8 input was a wakeup source #1 WUF9 Wakeup Flag For LLWU_P9 9 1 read-write 0 LLWU_P9 input was not a wakeup source #0 1 LLWU_P9 input was a wakeup source #1 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Specification Number 0 16 read-only 0 Standard features implemented #0 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only LPI2C0 The LPI2C Memory Map/Register Definition can be found here. LPI2C 0x0 0x0 0x174 registers n LPI2C0 14 MCCR0 Master Clock Configuration Register 0 0x48 32 read-write n 0x0 0x0 CLKHI Clock High Period 8 6 read-write CLKLO Clock Low Period 0 6 read-write DATAVD Data Valid Delay 24 6 read-write SETHOLD Setup Hold Delay 16 6 read-write MCCR1 Master Clock Configuration Register 1 0x50 32 read-write n 0x0 0x0 CLKHI Clock High Period 8 6 read-write CLKLO Clock Low Period 0 6 read-write DATAVD Data Valid Delay 24 6 read-write SETHOLD Setup Hold Delay 16 6 read-write MCFGR0 Master Configuration Register 0 0x20 32 read-write n 0x0 0x0 CIRFIFO Circular FIFO Enable 8 1 read-write 0 Circular FIFO is disabled. #0 1 Circular FIFO is enabled. #1 HREN Host Request Enable 0 1 read-write 0 Host request input is disabled. #0 1 Host request input is enabled. #1 HRPOL Host Request Polarity 1 1 read-write 0 Active low. #0 1 Active high. #1 HRSEL Host Request Select 2 1 read-write 0 Host request input is pin LPI2C_HREQ. #0 1 Host request input is input trigger. #1 RDMO Receive Data Match Only 9 1 read-write 0 Received data is stored in the receive FIFO as normal. #0 1 Received data is discarded unless the RMF is set. #1 MCFGR1 Master Configuration Register 1 0x24 32 read-write n 0x0 0x0 AUTOSTOP Automatic STOP Generation 8 1 read-write 0 No effect. #0 1 STOP condition is automatically generated whenever the transmit FIFO is empty and LPI2C master is busy. #1 IGNACK When set, the received NACK field is ignored and assumed to be ACK 9 1 read-write 0 LPI2C Master will receive ACK and NACK normally. #0 1 LPI2C Master will treat a received NACK as if it was an ACK. #1 MATCFG Match Configuration 16 3 read-write 000 Match disabled. #000 010 Match enabled (1st data word equals MATCH0 OR MATCH1). #010 011 Match enabled (any data word equals MATCH0 OR MATCH1). #011 100 Match enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1). #100 101 Match enabled (any data word equals MATCH0 AND next data word equals MATCH1). #101 110 Match enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1). #110 111 Match enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1). #111 PINCFG Pin Configuration 24 3 read-write 000 LPI2C configured for 2-pin open drain mode. #000 001 LPI2C configured for 2-pin output only mode (ultra-fast mode). #001 010 LPI2C configured for 2-pin push-pull mode. #010 011 LPI2C configured for 4-pin push-pull mode. #011 100 LPI2C configured for 2-pin open drain mode with separate LPI2C slave. #100 101 LPI2C configured for 2-pin output only mode (ultra-fast mode) with separate LPI2C slave. #101 110 LPI2C configured for 2-pin push-pull mode with separate LPI2C slave. #110 111 LPI2C configured for 4-pin push-pull mode (inverted outputs). #111 PRESCALE Prescaler 0 3 read-write 000 Divide by 1. #000 001 Divide by 2. #001 010 Divide by 4. #010 011 Divide by 8. #011 100 Divide by 16. #100 101 Divide by 32. #101 110 Divide by 64. #110 111 Divide by 128. #111 TIMECFG Timeout Configuration 10 1 read-write 0 Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout. #0 1 Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout. #1 MCFGR2 Master Configuration Register 2 0x28 32 read-write n 0x0 0x0 BUSIDLE Bus Idle Timeout 0 12 read-write FILTSCL Glitch Filter SCL 16 4 read-write FILTSDA Glitch Filter SDA 24 4 read-write MCFGR3 Master Configuration Register 3 0x2C 32 read-write n 0x0 0x0 PINLOW Pin Low Timeout 8 12 read-write MCR Master Control Register 0x10 32 read-write n 0x0 0x0 DBGEN Debug Enable 3 1 read-write 0 Master is disabled in debug mode. #0 1 Master is enabled in debug mode. #1 DOZEN Doze mode enable 2 1 read-write 0 Master is enabled in Doze mode. #0 1 Master is disabled in Doze mode. #1 MEN Master Enable 0 1 read-write 0 Master logic is disabled. #0 1 Master logic is enabled. #1 RRF Reset Receive FIFO 9 1 write-only 0 No effect. #0 1 Receive FIFO is reset. #1 RST Software Reset 1 1 read-write 0 Master logic is not reset. #0 1 Master logic is reset. #1 RTF Reset Transmit FIFO 8 1 write-only 0 No effect. #0 1 Transmit FIFO is reset. #1 MDER Master DMA Enable Register 0x1C 32 read-write n 0x0 0x0 RDDE Receive Data DMA Enable 1 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 TDDE Transmit Data DMA Enable 0 1 read-write 0 DMA request disabled. #0 1 DMA request enabled #1 MDMR Master Data Match Register 0x40 32 read-write n 0x0 0x0 MATCH0 Match 0 Value 0 8 read-write MATCH1 Match 1 Value 16 8 read-write MFCR Master FIFO Control Register 0x58 32 read-write n 0x0 0x0 RXWATER Receive FIFO Watermark 16 8 read-write TXWATER Transmit FIFO Watermark 0 8 read-write MFSR Master FIFO Status Register 0x5C 32 read-only n 0x0 0x0 RXCOUNT Receive FIFO Count 16 8 read-only TXCOUNT Transmit FIFO Count 0 8 read-only MIER Master Interrupt Enable Register 0x18 32 read-write n 0x0 0x0 ALIE Arbitration Lost Interrupt Enable 11 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 DMIE Data Match Interrupt Enable 14 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 EPIE End Packet Interrupt Enable 8 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 FEIE FIFO Error Interrupt Enable 12 1 read-write 0 Interrupt enabled. #0 1 Interrupt disabled. #1 NDIE NACK Detect Interrupt Enable 10 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 PLTIE Pin Low Timeout Interrupt Enable 13 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 RDIE Receive Data Interrupt Enable 1 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 SDIE STOP Detect Interrupt Enable 9 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 TDIE Transmit Data Interrupt Enable 0 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled #1 MRDR Master Receive Data Register 0x70 32 read-only n 0x0 0x0 DATA Receive Data 0 8 read-only RXEMPTY RX Empty 14 1 read-only 0 Receive FIFO is not empty. #0 1 Receive FIFO is empty. #1 MSR Master Status Register 0x14 32 read-write n 0x0 0x0 ALF Arbitration Lost Flag 11 1 read-write 0 Master has not lost arbitration. #0 1 Master has lost arbitration. #1 BBF Bus Busy Flag 25 1 read-only 0 I2C Bus is idle. #0 1 I2C Bus is busy. #1 DMF Data Match Flag 14 1 read-write 0 Have not received matching data. #0 1 Have received matching data. #1 EPF End Packet Flag 8 1 read-write 0 Master has not generated a STOP or Repeated START condition. #0 1 Master has generated a STOP or Repeated START condition. #1 FEF FIFO Error Flag 12 1 read-write 0 No error. #0 1 Master sending or receiving data without START condition. #1 MBF Master Busy Flag 24 1 read-only 0 I2C Master is idle. #0 1 I2C Master is busy. #1 NDF NACK Detect Flag 10 1 read-write 0 Unexpected NACK not detected. #0 1 Unexpected NACK was detected. #1 PLTF Pin Low Timeout Flag 13 1 read-write 0 Pin low timeout has not occurred or is disabled. #0 1 Pin low timeout has occurred. #1 RDF Receive Data Flag 1 1 read-only 0 Receive Data is not ready. #0 1 Receive data is ready. #1 SDF STOP Detect Flag 9 1 read-write 0 Master has not generated a STOP condition. #0 1 Master has generated a STOP condition. #1 TDF Transmit Data Flag 0 1 read-only 0 Transmit data not requested. #0 1 Transmit data is requested. #1 MTDR Master Transmit Data Register 0x60 32 write-only n 0x0 0x0 CMD Command Data 8 3 write-only 000 Transmit DATA[7:0]. #000 001 Receive (DATA[7:0] + 1) bytes. #001 010 Generate STOP condition. #010 011 Receive and discard (DATA[7:0] + 1) bytes. #011 100 Generate (repeated) START and transmit address in DATA[7:0]. #100 101 Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. #101 110 Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. #110 111 Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. #111 DATA Transmit Data 0 8 write-only PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 MRXFIFO Master Receive FIFO Size 8 4 read-only MTXFIFO Master Transmit FIFO Size 0 4 read-only SAMR Slave Address Match Register 0x140 32 read-write n 0x0 0x0 ADDR0 Address 0 Value 1 10 read-write ADDR1 Address 1 Value 17 10 read-write SASR Slave Address Status Register 0x150 32 read-only n 0x0 0x0 ANV Address Not Valid 14 1 read-only 0 RADDR is valid. #0 1 RADDR is not valid. #1 RADDR Received Address 0 11 read-only SCFGR1 Slave Configuration Register 1 0x124 32 read-write n 0x0 0x0 ACKSTALL ACK SCL Stall 3 1 read-write 0 Clock stretching disabled. #0 1 Clock stretching enabled. #1 ADDRCFG Address Configuration 16 3 read-write 000 Address match 0 (7-bit). #000 001 Address match 0 (10-bit). #001 010 Address match 0 (7-bit) or Address match 1 (7-bit). #010 011 Address match 0 (10-bit) or Address match 1 (10-bit). #011 100 Address match 0 (7-bit) or Address match 1 (10-bit). #100 101 Address match 0 (10-bit) or Address match 1 (7-bit). #101 110 From Address match 0 (7-bit) to Address match 1 (7-bit). #110 111 From Address match 0 (10-bit) to Address match 1 (10-bit). #111 ADRSTALL Address SCL Stall 0 1 read-write 0 Clock stretching disabled. #0 1 Clock stretching enabled. #1 GCEN General Call Enable 8 1 read-write 0 General Call address is disabled. #0 1 General call address is enabled. #1 HSMEN High Speed Mode Enable 13 1 read-write 0 Disables detection of Hs-mode master code. #0 1 Enables detection of Hs-mode master code. #1 IGNACK Ignore NACK 12 1 read-write 0 Slave will end transfer when NACK detected. #0 1 Slave will not end transfer when NACK detected. #1 RXCFG Receive Data Configuration 11 1 read-write 0 Reading the receive data register will return receive data and clear the receive data flag. #0 1 Reading the receive data register when the address valid flag is set will return the address status register and clear the address valid flag. Reading the receive data register when the address valid flag is clear will return receive data and clear the receive data flag. #1 RXSTALL RX SCL Stall 1 1 read-write 0 Clock stretching disabled. #0 1 Clock stretching enabled. #1 SAEN SMBus Alert Enable 9 1 read-write 0 Disables match on SMBus Alert. #0 1 Enables match on SMBus Alert. #1 TXCFG Transmit Flag Configuration 10 1 read-write 0 Transmit Data Flag will only assert during a slave-transmit transfer when the transmit data register is empty. #0 1 Transmit Data Flag will assert whenever the transmit data register is empty. #1 TXDSTALL TX Data SCL Stall 2 1 read-write 0 Clock stretching disabled. #0 1 Clock stretching enabled. #1 SCFGR2 Slave Configuration Register 2 0x128 32 read-write n 0x0 0x0 CLKHOLD Clock Hold Time 0 4 read-write DATAVD Data Valid Delay 8 6 read-write FILTSCL Glitch Filter SCL 16 4 read-write FILTSDA Glitch Filter SDA 24 4 read-write SCR Slave Control Register 0x110 32 read-write n 0x0 0x0 FILTDZ Filter Doze Enable 5 1 read-write 0 Filter remains enabled in Doze mode. #0 1 Filter is disabled in Doze mode. #1 FILTEN Filter Enable 4 1 read-write 0 Disable digital filter and output delay counter for slave mode. #0 1 Enable digital filter and output delay counter for slave mode. #1 RRF Reset Receive FIFO 9 1 write-only 0 No effect. #0 1 Receive Data Register is now empty. #1 RST Software Reset 1 1 read-write 0 Slave logic is not reset. #0 1 Slave logic is reset. #1 RTF Reset Transmit FIFO 8 1 write-only 0 No effect. #0 1 Transmit Data Register is now empty. #1 SEN Slave Enable 0 1 read-write 0 Slave mode is disabled. #0 1 Slave mode is enabled. #1 SDER Slave DMA Enable Register 0x11C 32 read-write n 0x0 0x0 AVDE Address Valid DMA Enable 2 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 RDDE Receive Data DMA Enable 1 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 TDDE Transmit Data DMA Enable 0 1 read-write 0 DMA request disabled. #0 1 DMA request enabled #1 SIER Slave Interrupt Enable Register 0x118 32 read-write n 0x0 0x0 AM0IE Address Match 0 Interrupt Enable 12 1 read-write 0 Interrupt enabled. #0 1 Interrupt disabled. #1 AM1F Address Match 1 Interrupt Enable 13 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 AVIE Address Valid Interrupt Enable 2 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 BEIE Bit Error Interrupt Enable 10 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 FEIE FIFO Error Interrupt Enable 11 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 GCIE General Call Interrupt Enable 14 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 RDIE Receive Data Interrupt Enable 1 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 RSIE Repeated Start Interrupt Enable 8 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 SARIE SMBus Alert Response Interrupt Enable 15 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 SDIE STOP Detect Interrupt Enable 9 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 TAIE Transmit ACK Interrupt Enable 3 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 TDIE Transmit Data Interrupt Enable 0 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled #1 SRDR Slave Receive Data Register 0x170 32 read-only n 0x0 0x0 DATA Receive Data 0 8 read-only RXEMPTY RX Empty 14 1 read-only 0 The Receive Data Register is not empty. #0 1 The Receive Data Register is empty. #1 SOF Start Of Frame 15 1 read-only 0 Indicates this is not the first data word since a (repeated) START or STOP condition. #0 1 Indicates this is the first data word since a (repeated) START or STOP condition. #1 SSR Slave Status Register 0x114 32 read-write n 0x0 0x0 AM0F Address Match 0 Flag 12 1 read-only 0 Have not received ADDR0 matching address. #0 1 Have received ADDR0 matching address. #1 AM1F Address Match 1 Flag 13 1 read-only 0 Have not received ADDR1 or ADDR0/ADDR1 range matching address. #0 1 Have received ADDR1 or ADDR0/ADDR1 range matching address. #1 AVF Address Valid Flag 2 1 read-only 0 Address Status Register is not valid. #0 1 Address Status Register is valid. #1 BBF Bus Busy Flag 25 1 read-only 0 I2C Bus is idle. #0 1 I2C Bus is busy. #1 BEF Bit Error Flag 10 1 read-write 0 Slave has not detected a bit error. #0 1 Slave has detected a bit error. #1 FEF FIFO Error Flag 11 1 read-write 0 FIFO underflow or overflow not detected. #0 1 FIFO underflow or overflow detected. #1 GCF General Call Flag 14 1 read-only 0 Slave has not detected the General Call Address or General Call Address disabled. #0 1 Slave has detected the General Call Address. #1 RDF Receive Data Flag 1 1 read-only 0 Receive Data is not ready. #0 1 Receive data is ready. #1 RSF Repeated Start Flag 8 1 read-write 0 Slave has not detected a Repeated START condition. #0 1 Slave has detected a Repeated START condition. #1 SARF SMBus Alert Response Flag 15 1 read-only 0 SMBus Alert Response disabled or not detected. #0 1 SMBus Alert Response enabled and detected. #1 SBF Slave Busy Flag 24 1 read-only 0 I2C Slave is idle. #0 1 I2C Slave is busy. #1 SDF STOP Detect Flag 9 1 read-write 0 Slave has not detected a STOP condition. #0 1 Slave has detected a STOP condition. #1 TAF Transmit ACK Flag 3 1 read-only 0 Transmit ACK/NACK is not required. #0 1 Transmit ACK/NACK is required. #1 TDF Transmit Data Flag 0 1 read-only 0 Transmit data not requested. #0 1 Transmit data is requested. #1 STAR Slave Transmit ACK Register 0x154 32 read-write n 0x0 0x0 TXNACK Transmit NACK 0 1 read-write 0 Transmit ACK for received word. #0 1 Transmit NACK for received word. #1 STDR Slave Transmit Data Register 0x160 32 write-only n 0x0 0x0 DATA Transmit Data 0 8 write-only VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Specification Number 0 16 read-only 10 Master only with standard feature set. #10 11 Master and slave with standard feature set. #11 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only LPI2C1 The LPI2C Memory Map/Register Definition can be found here. LPI2C 0x0 0x0 0x174 registers n LPI2C1 15 MCCR0 Master Clock Configuration Register 0 0x48 32 read-write n 0x0 0x0 CLKHI Clock High Period 8 6 read-write CLKLO Clock Low Period 0 6 read-write DATAVD Data Valid Delay 24 6 read-write SETHOLD Setup Hold Delay 16 6 read-write MCCR1 Master Clock Configuration Register 1 0x50 32 read-write n 0x0 0x0 CLKHI Clock High Period 8 6 read-write CLKLO Clock Low Period 0 6 read-write DATAVD Data Valid Delay 24 6 read-write SETHOLD Setup Hold Delay 16 6 read-write MCFGR0 Master Configuration Register 0 0x20 32 read-write n 0x0 0x0 CIRFIFO Circular FIFO Enable 8 1 read-write 0 Circular FIFO is disabled. #0 1 Circular FIFO is enabled. #1 HREN Host Request Enable 0 1 read-write 0 Host request input is disabled. #0 1 Host request input is enabled. #1 HRPOL Host Request Polarity 1 1 read-write 0 Active low. #0 1 Active high. #1 HRSEL Host Request Select 2 1 read-write 0 Host request input is pin LPI2C_HREQ. #0 1 Host request input is input trigger. #1 RDMO Receive Data Match Only 9 1 read-write 0 Received data is stored in the receive FIFO as normal. #0 1 Received data is discarded unless the RMF is set. #1 MCFGR1 Master Configuration Register 1 0x24 32 read-write n 0x0 0x0 AUTOSTOP Automatic STOP Generation 8 1 read-write 0 No effect. #0 1 STOP condition is automatically generated whenever the transmit FIFO is empty and LPI2C master is busy. #1 IGNACK When set, the received NACK field is ignored and assumed to be ACK 9 1 read-write 0 LPI2C Master will receive ACK and NACK normally. #0 1 LPI2C Master will treat a received NACK as if it was an ACK. #1 MATCFG Match Configuration 16 3 read-write 000 Match disabled. #000 010 Match enabled (1st data word equals MATCH0 OR MATCH1). #010 011 Match enabled (any data word equals MATCH0 OR MATCH1). #011 100 Match enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1). #100 101 Match enabled (any data word equals MATCH0 AND next data word equals MATCH1). #101 110 Match enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1). #110 111 Match enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1). #111 PINCFG Pin Configuration 24 3 read-write 000 LPI2C configured for 2-pin open drain mode. #000 001 LPI2C configured for 2-pin output only mode (ultra-fast mode). #001 010 LPI2C configured for 2-pin push-pull mode. #010 011 LPI2C configured for 4-pin push-pull mode. #011 100 LPI2C configured for 2-pin open drain mode with separate LPI2C slave. #100 101 LPI2C configured for 2-pin output only mode (ultra-fast mode) with separate LPI2C slave. #101 110 LPI2C configured for 2-pin push-pull mode with separate LPI2C slave. #110 111 LPI2C configured for 4-pin push-pull mode (inverted outputs). #111 PRESCALE Prescaler 0 3 read-write 000 Divide by 1. #000 001 Divide by 2. #001 010 Divide by 4. #010 011 Divide by 8. #011 100 Divide by 16. #100 101 Divide by 32. #101 110 Divide by 64. #110 111 Divide by 128. #111 TIMECFG Timeout Configuration 10 1 read-write 0 Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout. #0 1 Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout. #1 MCFGR2 Master Configuration Register 2 0x28 32 read-write n 0x0 0x0 BUSIDLE Bus Idle Timeout 0 12 read-write FILTSCL Glitch Filter SCL 16 4 read-write FILTSDA Glitch Filter SDA 24 4 read-write MCFGR3 Master Configuration Register 3 0x2C 32 read-write n 0x0 0x0 PINLOW Pin Low Timeout 8 12 read-write MCR Master Control Register 0x10 32 read-write n 0x0 0x0 DBGEN Debug Enable 3 1 read-write 0 Master is disabled in debug mode. #0 1 Master is enabled in debug mode. #1 DOZEN Doze mode enable 2 1 read-write 0 Master is enabled in Doze mode. #0 1 Master is disabled in Doze mode. #1 MEN Master Enable 0 1 read-write 0 Master logic is disabled. #0 1 Master logic is enabled. #1 RRF Reset Receive FIFO 9 1 write-only 0 No effect. #0 1 Receive FIFO is reset. #1 RST Software Reset 1 1 read-write 0 Master logic is not reset. #0 1 Master logic is reset. #1 RTF Reset Transmit FIFO 8 1 write-only 0 No effect. #0 1 Transmit FIFO is reset. #1 MDER Master DMA Enable Register 0x1C 32 read-write n 0x0 0x0 RDDE Receive Data DMA Enable 1 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 TDDE Transmit Data DMA Enable 0 1 read-write 0 DMA request disabled. #0 1 DMA request enabled #1 MDMR Master Data Match Register 0x40 32 read-write n 0x0 0x0 MATCH0 Match 0 Value 0 8 read-write MATCH1 Match 1 Value 16 8 read-write MFCR Master FIFO Control Register 0x58 32 read-write n 0x0 0x0 RXWATER Receive FIFO Watermark 16 8 read-write TXWATER Transmit FIFO Watermark 0 8 read-write MFSR Master FIFO Status Register 0x5C 32 read-only n 0x0 0x0 RXCOUNT Receive FIFO Count 16 8 read-only TXCOUNT Transmit FIFO Count 0 8 read-only MIER Master Interrupt Enable Register 0x18 32 read-write n 0x0 0x0 ALIE Arbitration Lost Interrupt Enable 11 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 DMIE Data Match Interrupt Enable 14 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 EPIE End Packet Interrupt Enable 8 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 FEIE FIFO Error Interrupt Enable 12 1 read-write 0 Interrupt enabled. #0 1 Interrupt disabled. #1 NDIE NACK Detect Interrupt Enable 10 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 PLTIE Pin Low Timeout Interrupt Enable 13 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 RDIE Receive Data Interrupt Enable 1 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 SDIE STOP Detect Interrupt Enable 9 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 TDIE Transmit Data Interrupt Enable 0 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled #1 MRDR Master Receive Data Register 0x70 32 read-only n 0x0 0x0 DATA Receive Data 0 8 read-only RXEMPTY RX Empty 14 1 read-only 0 Receive FIFO is not empty. #0 1 Receive FIFO is empty. #1 MSR Master Status Register 0x14 32 read-write n 0x0 0x0 ALF Arbitration Lost Flag 11 1 read-write 0 Master has not lost arbitration. #0 1 Master has lost arbitration. #1 BBF Bus Busy Flag 25 1 read-only 0 I2C Bus is idle. #0 1 I2C Bus is busy. #1 DMF Data Match Flag 14 1 read-write 0 Have not received matching data. #0 1 Have received matching data. #1 EPF End Packet Flag 8 1 read-write 0 Master has not generated a STOP or Repeated START condition. #0 1 Master has generated a STOP or Repeated START condition. #1 FEF FIFO Error Flag 12 1 read-write 0 No error. #0 1 Master sending or receiving data without START condition. #1 MBF Master Busy Flag 24 1 read-only 0 I2C Master is idle. #0 1 I2C Master is busy. #1 NDF NACK Detect Flag 10 1 read-write 0 Unexpected NACK not detected. #0 1 Unexpected NACK was detected. #1 PLTF Pin Low Timeout Flag 13 1 read-write 0 Pin low timeout has not occurred or is disabled. #0 1 Pin low timeout has occurred. #1 RDF Receive Data Flag 1 1 read-only 0 Receive Data is not ready. #0 1 Receive data is ready. #1 SDF STOP Detect Flag 9 1 read-write 0 Master has not generated a STOP condition. #0 1 Master has generated a STOP condition. #1 TDF Transmit Data Flag 0 1 read-only 0 Transmit data not requested. #0 1 Transmit data is requested. #1 MTDR Master Transmit Data Register 0x60 32 write-only n 0x0 0x0 CMD Command Data 8 3 write-only 000 Transmit DATA[7:0]. #000 001 Receive (DATA[7:0] + 1) bytes. #001 010 Generate STOP condition. #010 011 Receive and discard (DATA[7:0] + 1) bytes. #011 100 Generate (repeated) START and transmit address in DATA[7:0]. #100 101 Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. #101 110 Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. #110 111 Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. #111 DATA Transmit Data 0 8 write-only PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 MRXFIFO Master Receive FIFO Size 8 4 read-only MTXFIFO Master Transmit FIFO Size 0 4 read-only SAMR Slave Address Match Register 0x140 32 read-write n 0x0 0x0 ADDR0 Address 0 Value 1 10 read-write ADDR1 Address 1 Value 17 10 read-write SASR Slave Address Status Register 0x150 32 read-only n 0x0 0x0 ANV Address Not Valid 14 1 read-only 0 RADDR is valid. #0 1 RADDR is not valid. #1 RADDR Received Address 0 11 read-only SCFGR1 Slave Configuration Register 1 0x124 32 read-write n 0x0 0x0 ACKSTALL ACK SCL Stall 3 1 read-write 0 Clock stretching disabled. #0 1 Clock stretching enabled. #1 ADDRCFG Address Configuration 16 3 read-write 000 Address match 0 (7-bit). #000 001 Address match 0 (10-bit). #001 010 Address match 0 (7-bit) or Address match 1 (7-bit). #010 011 Address match 0 (10-bit) or Address match 1 (10-bit). #011 100 Address match 0 (7-bit) or Address match 1 (10-bit). #100 101 Address match 0 (10-bit) or Address match 1 (7-bit). #101 110 From Address match 0 (7-bit) to Address match 1 (7-bit). #110 111 From Address match 0 (10-bit) to Address match 1 (10-bit). #111 ADRSTALL Address SCL Stall 0 1 read-write 0 Clock stretching disabled. #0 1 Clock stretching enabled. #1 GCEN General Call Enable 8 1 read-write 0 General Call address is disabled. #0 1 General call address is enabled. #1 HSMEN High Speed Mode Enable 13 1 read-write 0 Disables detection of Hs-mode master code. #0 1 Enables detection of Hs-mode master code. #1 IGNACK Ignore NACK 12 1 read-write 0 Slave will end transfer when NACK detected. #0 1 Slave will not end transfer when NACK detected. #1 RXCFG Receive Data Configuration 11 1 read-write 0 Reading the receive data register will return receive data and clear the receive data flag. #0 1 Reading the receive data register when the address valid flag is set will return the address status register and clear the address valid flag. Reading the receive data register when the address valid flag is clear will return receive data and clear the receive data flag. #1 RXSTALL RX SCL Stall 1 1 read-write 0 Clock stretching disabled. #0 1 Clock stretching enabled. #1 SAEN SMBus Alert Enable 9 1 read-write 0 Disables match on SMBus Alert. #0 1 Enables match on SMBus Alert. #1 TXCFG Transmit Flag Configuration 10 1 read-write 0 Transmit Data Flag will only assert during a slave-transmit transfer when the transmit data register is empty. #0 1 Transmit Data Flag will assert whenever the transmit data register is empty. #1 TXDSTALL TX Data SCL Stall 2 1 read-write 0 Clock stretching disabled. #0 1 Clock stretching enabled. #1 SCFGR2 Slave Configuration Register 2 0x128 32 read-write n 0x0 0x0 CLKHOLD Clock Hold Time 0 4 read-write DATAVD Data Valid Delay 8 6 read-write FILTSCL Glitch Filter SCL 16 4 read-write FILTSDA Glitch Filter SDA 24 4 read-write SCR Slave Control Register 0x110 32 read-write n 0x0 0x0 FILTDZ Filter Doze Enable 5 1 read-write 0 Filter remains enabled in Doze mode. #0 1 Filter is disabled in Doze mode. #1 FILTEN Filter Enable 4 1 read-write 0 Disable digital filter and output delay counter for slave mode. #0 1 Enable digital filter and output delay counter for slave mode. #1 RRF Reset Receive FIFO 9 1 write-only 0 No effect. #0 1 Receive Data Register is now empty. #1 RST Software Reset 1 1 read-write 0 Slave logic is not reset. #0 1 Slave logic is reset. #1 RTF Reset Transmit FIFO 8 1 write-only 0 No effect. #0 1 Transmit Data Register is now empty. #1 SEN Slave Enable 0 1 read-write 0 Slave mode is disabled. #0 1 Slave mode is enabled. #1 SDER Slave DMA Enable Register 0x11C 32 read-write n 0x0 0x0 AVDE Address Valid DMA Enable 2 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 RDDE Receive Data DMA Enable 1 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 TDDE Transmit Data DMA Enable 0 1 read-write 0 DMA request disabled. #0 1 DMA request enabled #1 SIER Slave Interrupt Enable Register 0x118 32 read-write n 0x0 0x0 AM0IE Address Match 0 Interrupt Enable 12 1 read-write 0 Interrupt enabled. #0 1 Interrupt disabled. #1 AM1F Address Match 1 Interrupt Enable 13 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 AVIE Address Valid Interrupt Enable 2 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 BEIE Bit Error Interrupt Enable 10 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 FEIE FIFO Error Interrupt Enable 11 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 GCIE General Call Interrupt Enable 14 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 RDIE Receive Data Interrupt Enable 1 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 RSIE Repeated Start Interrupt Enable 8 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 SARIE SMBus Alert Response Interrupt Enable 15 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 SDIE STOP Detect Interrupt Enable 9 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 TAIE Transmit ACK Interrupt Enable 3 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 TDIE Transmit Data Interrupt Enable 0 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled #1 SRDR Slave Receive Data Register 0x170 32 read-only n 0x0 0x0 DATA Receive Data 0 8 read-only RXEMPTY RX Empty 14 1 read-only 0 The Receive Data Register is not empty. #0 1 The Receive Data Register is empty. #1 SOF Start Of Frame 15 1 read-only 0 Indicates this is not the first data word since a (repeated) START or STOP condition. #0 1 Indicates this is the first data word since a (repeated) START or STOP condition. #1 SSR Slave Status Register 0x114 32 read-write n 0x0 0x0 AM0F Address Match 0 Flag 12 1 read-only 0 Have not received ADDR0 matching address. #0 1 Have received ADDR0 matching address. #1 AM1F Address Match 1 Flag 13 1 read-only 0 Have not received ADDR1 or ADDR0/ADDR1 range matching address. #0 1 Have received ADDR1 or ADDR0/ADDR1 range matching address. #1 AVF Address Valid Flag 2 1 read-only 0 Address Status Register is not valid. #0 1 Address Status Register is valid. #1 BBF Bus Busy Flag 25 1 read-only 0 I2C Bus is idle. #0 1 I2C Bus is busy. #1 BEF Bit Error Flag 10 1 read-write 0 Slave has not detected a bit error. #0 1 Slave has detected a bit error. #1 FEF FIFO Error Flag 11 1 read-write 0 FIFO underflow or overflow not detected. #0 1 FIFO underflow or overflow detected. #1 GCF General Call Flag 14 1 read-only 0 Slave has not detected the General Call Address or General Call Address disabled. #0 1 Slave has detected the General Call Address. #1 RDF Receive Data Flag 1 1 read-only 0 Receive Data is not ready. #0 1 Receive data is ready. #1 RSF Repeated Start Flag 8 1 read-write 0 Slave has not detected a Repeated START condition. #0 1 Slave has detected a Repeated START condition. #1 SARF SMBus Alert Response Flag 15 1 read-only 0 SMBus Alert Response disabled or not detected. #0 1 SMBus Alert Response enabled and detected. #1 SBF Slave Busy Flag 24 1 read-only 0 I2C Slave is idle. #0 1 I2C Slave is busy. #1 SDF STOP Detect Flag 9 1 read-write 0 Slave has not detected a STOP condition. #0 1 Slave has detected a STOP condition. #1 TAF Transmit ACK Flag 3 1 read-only 0 Transmit ACK/NACK is not required. #0 1 Transmit ACK/NACK is required. #1 TDF Transmit Data Flag 0 1 read-only 0 Transmit data not requested. #0 1 Transmit data is requested. #1 STAR Slave Transmit ACK Register 0x154 32 read-write n 0x0 0x0 TXNACK Transmit NACK 0 1 read-write 0 Transmit ACK for received word. #0 1 Transmit NACK for received word. #1 STDR Slave Transmit Data Register 0x160 32 write-only n 0x0 0x0 DATA Transmit Data 0 8 write-only VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Specification Number 0 16 read-only 10 Master only with standard feature set. #10 11 Master and slave with standard feature set. #11 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only LPI2C2 The LPI2C Memory Map/Register Definition can be found here. LPI2C 0x0 0x0 0x174 registers n LPI2C2 39 MCCR0 Master Clock Configuration Register 0 0x48 32 read-write n 0x0 0x0 CLKHI Clock High Period 8 6 read-write CLKLO Clock Low Period 0 6 read-write DATAVD Data Valid Delay 24 6 read-write SETHOLD Setup Hold Delay 16 6 read-write MCCR1 Master Clock Configuration Register 1 0x50 32 read-write n 0x0 0x0 CLKHI Clock High Period 8 6 read-write CLKLO Clock Low Period 0 6 read-write DATAVD Data Valid Delay 24 6 read-write SETHOLD Setup Hold Delay 16 6 read-write MCFGR0 Master Configuration Register 0 0x20 32 read-write n 0x0 0x0 CIRFIFO Circular FIFO Enable 8 1 read-write 0 Circular FIFO is disabled. #0 1 Circular FIFO is enabled. #1 HREN Host Request Enable 0 1 read-write 0 Host request input is disabled. #0 1 Host request input is enabled. #1 HRPOL Host Request Polarity 1 1 read-write 0 Active low. #0 1 Active high. #1 HRSEL Host Request Select 2 1 read-write 0 Host request input is pin LPI2C_HREQ. #0 1 Host request input is input trigger. #1 RDMO Receive Data Match Only 9 1 read-write 0 Received data is stored in the receive FIFO as normal. #0 1 Received data is discarded unless the RMF is set. #1 MCFGR1 Master Configuration Register 1 0x24 32 read-write n 0x0 0x0 AUTOSTOP Automatic STOP Generation 8 1 read-write 0 No effect. #0 1 STOP condition is automatically generated whenever the transmit FIFO is empty and LPI2C master is busy. #1 IGNACK When set, the received NACK field is ignored and assumed to be ACK 9 1 read-write 0 LPI2C Master will receive ACK and NACK normally. #0 1 LPI2C Master will treat a received NACK as if it was an ACK. #1 MATCFG Match Configuration 16 3 read-write 000 Match disabled. #000 010 Match enabled (1st data word equals MATCH0 OR MATCH1). #010 011 Match enabled (any data word equals MATCH0 OR MATCH1). #011 100 Match enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1). #100 101 Match enabled (any data word equals MATCH0 AND next data word equals MATCH1). #101 110 Match enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1). #110 111 Match enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1). #111 PINCFG Pin Configuration 24 3 read-write 000 LPI2C configured for 2-pin open drain mode. #000 001 LPI2C configured for 2-pin output only mode (ultra-fast mode). #001 010 LPI2C configured for 2-pin push-pull mode. #010 011 LPI2C configured for 4-pin push-pull mode. #011 100 LPI2C configured for 2-pin open drain mode with separate LPI2C slave. #100 101 LPI2C configured for 2-pin output only mode (ultra-fast mode) with separate LPI2C slave. #101 110 LPI2C configured for 2-pin push-pull mode with separate LPI2C slave. #110 111 LPI2C configured for 4-pin push-pull mode (inverted outputs). #111 PRESCALE Prescaler 0 3 read-write 000 Divide by 1. #000 001 Divide by 2. #001 010 Divide by 4. #010 011 Divide by 8. #011 100 Divide by 16. #100 101 Divide by 32. #101 110 Divide by 64. #110 111 Divide by 128. #111 TIMECFG Timeout Configuration 10 1 read-write 0 Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout. #0 1 Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout. #1 MCFGR2 Master Configuration Register 2 0x28 32 read-write n 0x0 0x0 BUSIDLE Bus Idle Timeout 0 12 read-write FILTSCL Glitch Filter SCL 16 4 read-write FILTSDA Glitch Filter SDA 24 4 read-write MCFGR3 Master Configuration Register 3 0x2C 32 read-write n 0x0 0x0 PINLOW Pin Low Timeout 8 12 read-write MCR Master Control Register 0x10 32 read-write n 0x0 0x0 DBGEN Debug Enable 3 1 read-write 0 Master is disabled in debug mode. #0 1 Master is enabled in debug mode. #1 DOZEN Doze mode enable 2 1 read-write 0 Master is enabled in Doze mode. #0 1 Master is disabled in Doze mode. #1 MEN Master Enable 0 1 read-write 0 Master logic is disabled. #0 1 Master logic is enabled. #1 RRF Reset Receive FIFO 9 1 write-only 0 No effect. #0 1 Receive FIFO is reset. #1 RST Software Reset 1 1 read-write 0 Master logic is not reset. #0 1 Master logic is reset. #1 RTF Reset Transmit FIFO 8 1 write-only 0 No effect. #0 1 Transmit FIFO is reset. #1 MDER Master DMA Enable Register 0x1C 32 read-write n 0x0 0x0 RDDE Receive Data DMA Enable 1 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 TDDE Transmit Data DMA Enable 0 1 read-write 0 DMA request disabled. #0 1 DMA request enabled #1 MDMR Master Data Match Register 0x40 32 read-write n 0x0 0x0 MATCH0 Match 0 Value 0 8 read-write MATCH1 Match 1 Value 16 8 read-write MFCR Master FIFO Control Register 0x58 32 read-write n 0x0 0x0 RXWATER Receive FIFO Watermark 16 8 read-write TXWATER Transmit FIFO Watermark 0 8 read-write MFSR Master FIFO Status Register 0x5C 32 read-only n 0x0 0x0 RXCOUNT Receive FIFO Count 16 8 read-only TXCOUNT Transmit FIFO Count 0 8 read-only MIER Master Interrupt Enable Register 0x18 32 read-write n 0x0 0x0 ALIE Arbitration Lost Interrupt Enable 11 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 DMIE Data Match Interrupt Enable 14 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 EPIE End Packet Interrupt Enable 8 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 FEIE FIFO Error Interrupt Enable 12 1 read-write 0 Interrupt enabled. #0 1 Interrupt disabled. #1 NDIE NACK Detect Interrupt Enable 10 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 PLTIE Pin Low Timeout Interrupt Enable 13 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 RDIE Receive Data Interrupt Enable 1 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 SDIE STOP Detect Interrupt Enable 9 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 TDIE Transmit Data Interrupt Enable 0 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled #1 MRDR Master Receive Data Register 0x70 32 read-only n 0x0 0x0 DATA Receive Data 0 8 read-only RXEMPTY RX Empty 14 1 read-only 0 Receive FIFO is not empty. #0 1 Receive FIFO is empty. #1 MSR Master Status Register 0x14 32 read-write n 0x0 0x0 ALF Arbitration Lost Flag 11 1 read-write 0 Master has not lost arbitration. #0 1 Master has lost arbitration. #1 BBF Bus Busy Flag 25 1 read-only 0 I2C Bus is idle. #0 1 I2C Bus is busy. #1 DMF Data Match Flag 14 1 read-write 0 Have not received matching data. #0 1 Have received matching data. #1 EPF End Packet Flag 8 1 read-write 0 Master has not generated a STOP or Repeated START condition. #0 1 Master has generated a STOP or Repeated START condition. #1 FEF FIFO Error Flag 12 1 read-write 0 No error. #0 1 Master sending or receiving data without START condition. #1 MBF Master Busy Flag 24 1 read-only 0 I2C Master is idle. #0 1 I2C Master is busy. #1 NDF NACK Detect Flag 10 1 read-write 0 Unexpected NACK not detected. #0 1 Unexpected NACK was detected. #1 PLTF Pin Low Timeout Flag 13 1 read-write 0 Pin low timeout has not occurred or is disabled. #0 1 Pin low timeout has occurred. #1 RDF Receive Data Flag 1 1 read-only 0 Receive Data is not ready. #0 1 Receive data is ready. #1 SDF STOP Detect Flag 9 1 read-write 0 Master has not generated a STOP condition. #0 1 Master has generated a STOP condition. #1 TDF Transmit Data Flag 0 1 read-only 0 Transmit data not requested. #0 1 Transmit data is requested. #1 MTDR Master Transmit Data Register 0x60 32 write-only n 0x0 0x0 CMD Command Data 8 3 write-only 000 Transmit DATA[7:0]. #000 001 Receive (DATA[7:0] + 1) bytes. #001 010 Generate STOP condition. #010 011 Receive and discard (DATA[7:0] + 1) bytes. #011 100 Generate (repeated) START and transmit address in DATA[7:0]. #100 101 Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. #101 110 Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. #110 111 Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. #111 DATA Transmit Data 0 8 write-only PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 MRXFIFO Master Receive FIFO Size 8 4 read-only MTXFIFO Master Transmit FIFO Size 0 4 read-only SAMR Slave Address Match Register 0x140 32 read-write n 0x0 0x0 ADDR0 Address 0 Value 1 10 read-write ADDR1 Address 1 Value 17 10 read-write SASR Slave Address Status Register 0x150 32 read-only n 0x0 0x0 ANV Address Not Valid 14 1 read-only 0 RADDR is valid. #0 1 RADDR is not valid. #1 RADDR Received Address 0 11 read-only SCFGR1 Slave Configuration Register 1 0x124 32 read-write n 0x0 0x0 ACKSTALL ACK SCL Stall 3 1 read-write 0 Clock stretching disabled. #0 1 Clock stretching enabled. #1 ADDRCFG Address Configuration 16 3 read-write 000 Address match 0 (7-bit). #000 001 Address match 0 (10-bit). #001 010 Address match 0 (7-bit) or Address match 1 (7-bit). #010 011 Address match 0 (10-bit) or Address match 1 (10-bit). #011 100 Address match 0 (7-bit) or Address match 1 (10-bit). #100 101 Address match 0 (10-bit) or Address match 1 (7-bit). #101 110 From Address match 0 (7-bit) to Address match 1 (7-bit). #110 111 From Address match 0 (10-bit) to Address match 1 (10-bit). #111 ADRSTALL Address SCL Stall 0 1 read-write 0 Clock stretching disabled. #0 1 Clock stretching enabled. #1 GCEN General Call Enable 8 1 read-write 0 General Call address is disabled. #0 1 General call address is enabled. #1 HSMEN High Speed Mode Enable 13 1 read-write 0 Disables detection of Hs-mode master code. #0 1 Enables detection of Hs-mode master code. #1 IGNACK Ignore NACK 12 1 read-write 0 Slave will end transfer when NACK detected. #0 1 Slave will not end transfer when NACK detected. #1 RXCFG Receive Data Configuration 11 1 read-write 0 Reading the receive data register will return receive data and clear the receive data flag. #0 1 Reading the receive data register when the address valid flag is set will return the address status register and clear the address valid flag. Reading the receive data register when the address valid flag is clear will return receive data and clear the receive data flag. #1 RXSTALL RX SCL Stall 1 1 read-write 0 Clock stretching disabled. #0 1 Clock stretching enabled. #1 SAEN SMBus Alert Enable 9 1 read-write 0 Disables match on SMBus Alert. #0 1 Enables match on SMBus Alert. #1 TXCFG Transmit Flag Configuration 10 1 read-write 0 Transmit Data Flag will only assert during a slave-transmit transfer when the transmit data register is empty. #0 1 Transmit Data Flag will assert whenever the transmit data register is empty. #1 TXDSTALL TX Data SCL Stall 2 1 read-write 0 Clock stretching disabled. #0 1 Clock stretching enabled. #1 SCFGR2 Slave Configuration Register 2 0x128 32 read-write n 0x0 0x0 CLKHOLD Clock Hold Time 0 4 read-write DATAVD Data Valid Delay 8 6 read-write FILTSCL Glitch Filter SCL 16 4 read-write FILTSDA Glitch Filter SDA 24 4 read-write SCR Slave Control Register 0x110 32 read-write n 0x0 0x0 FILTDZ Filter Doze Enable 5 1 read-write 0 Filter remains enabled in Doze mode. #0 1 Filter is disabled in Doze mode. #1 FILTEN Filter Enable 4 1 read-write 0 Disable digital filter and output delay counter for slave mode. #0 1 Enable digital filter and output delay counter for slave mode. #1 RRF Reset Receive FIFO 9 1 write-only 0 No effect. #0 1 Receive Data Register is now empty. #1 RST Software Reset 1 1 read-write 0 Slave logic is not reset. #0 1 Slave logic is reset. #1 RTF Reset Transmit FIFO 8 1 write-only 0 No effect. #0 1 Transmit Data Register is now empty. #1 SEN Slave Enable 0 1 read-write 0 Slave mode is disabled. #0 1 Slave mode is enabled. #1 SDER Slave DMA Enable Register 0x11C 32 read-write n 0x0 0x0 AVDE Address Valid DMA Enable 2 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 RDDE Receive Data DMA Enable 1 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 TDDE Transmit Data DMA Enable 0 1 read-write 0 DMA request disabled. #0 1 DMA request enabled #1 SIER Slave Interrupt Enable Register 0x118 32 read-write n 0x0 0x0 AM0IE Address Match 0 Interrupt Enable 12 1 read-write 0 Interrupt enabled. #0 1 Interrupt disabled. #1 AM1F Address Match 1 Interrupt Enable 13 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 AVIE Address Valid Interrupt Enable 2 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 BEIE Bit Error Interrupt Enable 10 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 FEIE FIFO Error Interrupt Enable 11 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 GCIE General Call Interrupt Enable 14 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 RDIE Receive Data Interrupt Enable 1 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 RSIE Repeated Start Interrupt Enable 8 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 SARIE SMBus Alert Response Interrupt Enable 15 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 SDIE STOP Detect Interrupt Enable 9 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 TAIE Transmit ACK Interrupt Enable 3 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 TDIE Transmit Data Interrupt Enable 0 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled #1 SRDR Slave Receive Data Register 0x170 32 read-only n 0x0 0x0 DATA Receive Data 0 8 read-only RXEMPTY RX Empty 14 1 read-only 0 The Receive Data Register is not empty. #0 1 The Receive Data Register is empty. #1 SOF Start Of Frame 15 1 read-only 0 Indicates this is not the first data word since a (repeated) START or STOP condition. #0 1 Indicates this is the first data word since a (repeated) START or STOP condition. #1 SSR Slave Status Register 0x114 32 read-write n 0x0 0x0 AM0F Address Match 0 Flag 12 1 read-only 0 Have not received ADDR0 matching address. #0 1 Have received ADDR0 matching address. #1 AM1F Address Match 1 Flag 13 1 read-only 0 Have not received ADDR1 or ADDR0/ADDR1 range matching address. #0 1 Have received ADDR1 or ADDR0/ADDR1 range matching address. #1 AVF Address Valid Flag 2 1 read-only 0 Address Status Register is not valid. #0 1 Address Status Register is valid. #1 BBF Bus Busy Flag 25 1 read-only 0 I2C Bus is idle. #0 1 I2C Bus is busy. #1 BEF Bit Error Flag 10 1 read-write 0 Slave has not detected a bit error. #0 1 Slave has detected a bit error. #1 FEF FIFO Error Flag 11 1 read-write 0 FIFO underflow or overflow not detected. #0 1 FIFO underflow or overflow detected. #1 GCF General Call Flag 14 1 read-only 0 Slave has not detected the General Call Address or General Call Address disabled. #0 1 Slave has detected the General Call Address. #1 RDF Receive Data Flag 1 1 read-only 0 Receive Data is not ready. #0 1 Receive data is ready. #1 RSF Repeated Start Flag 8 1 read-write 0 Slave has not detected a Repeated START condition. #0 1 Slave has detected a Repeated START condition. #1 SARF SMBus Alert Response Flag 15 1 read-only 0 SMBus Alert Response disabled or not detected. #0 1 SMBus Alert Response enabled and detected. #1 SBF Slave Busy Flag 24 1 read-only 0 I2C Slave is idle. #0 1 I2C Slave is busy. #1 SDF STOP Detect Flag 9 1 read-write 0 Slave has not detected a STOP condition. #0 1 Slave has detected a STOP condition. #1 TAF Transmit ACK Flag 3 1 read-only 0 Transmit ACK/NACK is not required. #0 1 Transmit ACK/NACK is required. #1 TDF Transmit Data Flag 0 1 read-only 0 Transmit data not requested. #0 1 Transmit data is requested. #1 STAR Slave Transmit ACK Register 0x154 32 read-write n 0x0 0x0 TXNACK Transmit NACK 0 1 read-write 0 Transmit ACK for received word. #0 1 Transmit NACK for received word. #1 STDR Slave Transmit Data Register 0x160 32 write-only n 0x0 0x0 DATA Transmit Data 0 8 write-only VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Specification Number 0 16 read-only 10 Master only with standard feature set. #10 11 Master and slave with standard feature set. #11 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only LPIT0 Low Power Periodic Interrupt Timer (LPIT) LPIT 0x0 0x0 0x5C registers n LPIT0 9 CLRTEN Clear Timer Enable Register 0x18 32 read-write n 0x0 0x0 CLR_T_EN_0 Clear Timer 0 Enable 0 1 write-only 0 No action #0 1 Clear T_EN bit for Timer Channel 0 #1 CLR_T_EN_1 Clear Timer 1 Enable 1 1 write-only 0 No Action #0 1 Clear T_EN bit for Timer Channel 1 #1 CLR_T_EN_2 Clear Timer 2 Enable 2 1 write-only 0 No Action #0 1 Clear T_EN bit for Timer Channel 2 #1 CLR_T_EN_3 Clear Timer 3 Enable 3 1 write-only 0 No Action #0 1 Clear T_EN bit for Timer Channel 3 #1 CVAL0 Current Timer Value 0x48 32 read-only n 0x0 0x0 TMR_CUR_VAL Current Timer Value 0 32 read-only CVAL1 Current Timer Value 0x7C 32 read-only n 0x0 0x0 TMR_CUR_VAL Current Timer Value 0 32 read-only CVAL2 Current Timer Value 0xC0 32 read-only n 0x0 0x0 TMR_CUR_VAL Current Timer Value 0 32 read-only CVAL3 Current Timer Value 0x114 32 read-only n 0x0 0x0 TMR_CUR_VAL Current Timer Value 0 32 read-only MCR Module Control Register 0x8 32 read-write n 0x0 0x0 DBG_EN Debug Enable Bit 3 1 read-write 0 Timer channels are stopped in Debug mode #0 1 Timer channels continue to run in Debug mode #1 DOZE_EN DOZE Mode Enable Bit 2 1 read-write 0 Timer channels are stopped in DOZE mode #0 1 Timer channels continue to run in DOZE mode #1 M_CEN Module Clock Enable 0 1 read-write 0 Protocol clock to timers is disabled #0 1 Protocol clock to timers is enabled #1 SW_RST Software Reset Bit 1 1 read-write 0 Timer channels and registers are not reset #0 1 Timer channels and registers are reset #1 MIER Module Interrupt Enable Register 0x10 32 read-write n 0x0 0x0 TIE0 Channel 0 Timer Interrupt Enable 0 1 read-write 0 Interrupt generation is disabled #0 1 Interrupt generation is enabled #1 TIE1 Channel 1 Timer Interrupt Enable 1 1 read-write 0 Interrupt generation is disabled #0 1 Interrupt generation is enabled #1 TIE2 Channel 2 Timer Interrupt Enable 2 1 read-write 0 Interrupt generation is disabled #0 1 Interrupt generation is enabled #1 TIE3 Channel 3 Timer Interrupt Enable 3 1 read-write 0 Interrupt generation is disabled #0 1 Interrupt generation is enabled #1 MSR Module Status Register 0xC 32 read-write n 0x0 0x0 TIF0 Channel 0 Timer Interrupt Flag 0 1 read-write 0 Timer has not timed out #0 1 Timeout has occurred #1 TIF1 Channel 1 Timer Interrupt Flag 1 1 read-write 0 Timer has not timed out #0 1 Timeout has occurred #1 TIF2 Channel 2 Timer Interrupt Flag 2 1 read-write 0 Timer has not timed out #0 1 Timeout has occurred #1 TIF3 Channel 3 Timer Interrupt Flag 3 1 read-write 0 Timer has not timed out #0 1 Timeout has occurred #1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 CHANNEL Number of Timer Channels 0 8 read-only EXT_TRIG Number of External Trigger Inputs 8 8 read-only SETTEN Set Timer Enable Register 0x14 32 read-write n 0x0 0x0 SET_T_EN_0 Set Timer 0 Enable 0 1 read-write 0 No effect #0 1 Enables the Timer Channel 0 #1 SET_T_EN_1 Set Timer 1 Enable 1 1 read-write 0 No Effect #0 1 Enables the Timer Channel 1 #1 SET_T_EN_2 Set Timer 2 Enable 2 1 read-write 0 No Effect #0 1 Enables the Timer Channel 2 #1 SET_T_EN_3 Set Timer 3 Enable 3 1 read-write 0 No effect #0 1 Enables the Timer Channel 3 #1 TCTRL0 Timer Control Register 0x50 32 read-write n 0x0 0x0 CHAIN Chain Channel 1 1 read-write 0 Channel Chaining is disabled. Channel Timer runs independently. #0 1 Channel Chaining is enabled. Timer decrements on previous channel's timeout #1 MODE Timer Operation Mode 2 2 read-write 00 32-bit Periodic Counter #00 01 Dual 16-bit Periodic Counter #01 10 32-bit Trigger Accumulator #10 11 32-bit Trigger Input Capture #11 TRG_SEL Trigger Select 24 4 read-write 0 Timer channel 0 trigger source is selected #0000 1 Timer channel 1 trigger source is selected #0001 10 Timer channel 2 trigger source is selected #0010 TRG_SRC Trigger Source 23 1 read-write 0 Trigger source selected in external #0 1 Trigger source selected is the internal trigger #1 TROT Timer Reload On Trigger 18 1 read-write 0 Timer will not reload on selected trigger #0 1 Timer will reload on selected trigger #1 TSOI Timer Stop On Interrupt 17 1 read-write 0 Timer does not stop after timeout #0 1 Timer will stop after timeout and will restart after rising edge on the T_EN bit is detected (i.e. timer channel is disabled and then enabled) #1 TSOT Timer Start On Trigger 16 1 read-write 0 Timer starts to decrement immediately based on restart condition (controlled by TSOI bit) #0 1 Timer starts to decrement when rising edge on selected trigger is detected #1 T_EN Timer Enable 0 1 read-write 0 Timer Channel is disabled #0 1 Timer Channel is enabled #1 TCTRL1 Timer Control Register 0x88 32 read-write n 0x0 0x0 CHAIN Chain Channel 1 1 read-write 0 Channel Chaining is disabled. Channel Timer runs independently. #0 1 Channel Chaining is enabled. Timer decrements on previous channel's timeout #1 MODE Timer Operation Mode 2 2 read-write 00 32-bit Periodic Counter #00 01 Dual 16-bit Periodic Counter #01 10 32-bit Trigger Accumulator #10 11 32-bit Trigger Input Capture #11 TRG_SEL Trigger Select 24 4 read-write 0 Timer channel 0 trigger source is selected #0000 1 Timer channel 1 trigger source is selected #0001 10 Timer channel 2 trigger source is selected #0010 TRG_SRC Trigger Source 23 1 read-write 0 Trigger source selected in external #0 1 Trigger source selected is the internal trigger #1 TROT Timer Reload On Trigger 18 1 read-write 0 Timer will not reload on selected trigger #0 1 Timer will reload on selected trigger #1 TSOI Timer Stop On Interrupt 17 1 read-write 0 Timer does not stop after timeout #0 1 Timer will stop after timeout and will restart after rising edge on the T_EN bit is detected (i.e. timer channel is disabled and then enabled) #1 TSOT Timer Start On Trigger 16 1 read-write 0 Timer starts to decrement immediately based on restart condition (controlled by TSOI bit) #0 1 Timer starts to decrement when rising edge on selected trigger is detected #1 T_EN Timer Enable 0 1 read-write 0 Timer Channel is disabled #0 1 Timer Channel is enabled #1 TCTRL2 Timer Control Register 0xD0 32 read-write n 0x0 0x0 CHAIN Chain Channel 1 1 read-write 0 Channel Chaining is disabled. Channel Timer runs independently. #0 1 Channel Chaining is enabled. Timer decrements on previous channel's timeout #1 MODE Timer Operation Mode 2 2 read-write 00 32-bit Periodic Counter #00 01 Dual 16-bit Periodic Counter #01 10 32-bit Trigger Accumulator #10 11 32-bit Trigger Input Capture #11 TRG_SEL Trigger Select 24 4 read-write 0 Timer channel 0 trigger source is selected #0000 1 Timer channel 1 trigger source is selected #0001 10 Timer channel 2 trigger source is selected #0010 TRG_SRC Trigger Source 23 1 read-write 0 Trigger source selected in external #0 1 Trigger source selected is the internal trigger #1 TROT Timer Reload On Trigger 18 1 read-write 0 Timer will not reload on selected trigger #0 1 Timer will reload on selected trigger #1 TSOI Timer Stop On Interrupt 17 1 read-write 0 Timer does not stop after timeout #0 1 Timer will stop after timeout and will restart after rising edge on the T_EN bit is detected (i.e. timer channel is disabled and then enabled) #1 TSOT Timer Start On Trigger 16 1 read-write 0 Timer starts to decrement immediately based on restart condition (controlled by TSOI bit) #0 1 Timer starts to decrement when rising edge on selected trigger is detected #1 T_EN Timer Enable 0 1 read-write 0 Timer Channel is disabled #0 1 Timer Channel is enabled #1 TCTRL3 Timer Control Register 0x128 32 read-write n 0x0 0x0 CHAIN Chain Channel 1 1 read-write 0 Channel Chaining is disabled. Channel Timer runs independently. #0 1 Channel Chaining is enabled. Timer decrements on previous channel's timeout #1 MODE Timer Operation Mode 2 2 read-write 00 32-bit Periodic Counter #00 01 Dual 16-bit Periodic Counter #01 10 32-bit Trigger Accumulator #10 11 32-bit Trigger Input Capture #11 TRG_SEL Trigger Select 24 4 read-write 0 Timer channel 0 trigger source is selected #0000 1 Timer channel 1 trigger source is selected #0001 10 Timer channel 2 trigger source is selected #0010 TRG_SRC Trigger Source 23 1 read-write 0 Trigger source selected in external #0 1 Trigger source selected is the internal trigger #1 TROT Timer Reload On Trigger 18 1 read-write 0 Timer will not reload on selected trigger #0 1 Timer will reload on selected trigger #1 TSOI Timer Stop On Interrupt 17 1 read-write 0 Timer does not stop after timeout #0 1 Timer will stop after timeout and will restart after rising edge on the T_EN bit is detected (i.e. timer channel is disabled and then enabled) #1 TSOT Timer Start On Trigger 16 1 read-write 0 Timer starts to decrement immediately based on restart condition (controlled by TSOI bit) #0 1 Timer starts to decrement when rising edge on selected trigger is detected #1 T_EN Timer Enable 0 1 read-write 0 Timer Channel is disabled #0 1 Timer Channel is enabled #1 TVAL0 Timer Value Register 0x40 32 read-write n 0x0 0x0 TMR_VAL Timer Value 0 32 read-write 0 Invalid load value in compare modes #0 TVAL1 Timer Value Register 0x70 32 read-write n 0x0 0x0 TMR_VAL Timer Value 0 32 read-write 0 Invalid load value in compare modes #0 TVAL2 Timer Value Register 0xB0 32 read-write n 0x0 0x0 TMR_VAL Timer Value 0 32 read-write 0 Invalid load value in compare modes #0 TVAL3 Timer Value Register 0x100 32 read-write n 0x0 0x0 TMR_VAL Timer Value 0 32 read-write 0 Invalid load value in compare modes #0 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Number 0 16 read-only MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only LPIT1 Low Power Periodic Interrupt Timer (LPIT) LPIT 0x0 0x0 0x5C registers n LPIT1 33 CLRTEN Clear Timer Enable Register 0x18 32 read-write n 0x0 0x0 CLR_T_EN_0 Clear Timer 0 Enable 0 1 write-only 0 No action #0 1 Clear T_EN bit for Timer Channel 0 #1 CLR_T_EN_1 Clear Timer 1 Enable 1 1 write-only 0 No Action #0 1 Clear T_EN bit for Timer Channel 1 #1 CLR_T_EN_2 Clear Timer 2 Enable 2 1 write-only 0 No Action #0 1 Clear T_EN bit for Timer Channel 2 #1 CLR_T_EN_3 Clear Timer 3 Enable 3 1 write-only 0 No Action #0 1 Clear T_EN bit for Timer Channel 3 #1 CVAL0 Current Timer Value 0x48 32 read-only n 0x0 0x0 TMR_CUR_VAL Current Timer Value 0 32 read-only CVAL1 Current Timer Value 0x7C 32 read-only n 0x0 0x0 TMR_CUR_VAL Current Timer Value 0 32 read-only CVAL2 Current Timer Value 0xC0 32 read-only n 0x0 0x0 TMR_CUR_VAL Current Timer Value 0 32 read-only CVAL3 Current Timer Value 0x114 32 read-only n 0x0 0x0 TMR_CUR_VAL Current Timer Value 0 32 read-only MCR Module Control Register 0x8 32 read-write n 0x0 0x0 DBG_EN Debug Enable Bit 3 1 read-write 0 Timer channels are stopped in Debug mode #0 1 Timer channels continue to run in Debug mode #1 DOZE_EN DOZE Mode Enable Bit 2 1 read-write 0 Timer channels are stopped in DOZE mode #0 1 Timer channels continue to run in DOZE mode #1 M_CEN Module Clock Enable 0 1 read-write 0 Protocol clock to timers is disabled #0 1 Protocol clock to timers is enabled #1 SW_RST Software Reset Bit 1 1 read-write 0 Timer channels and registers are not reset #0 1 Timer channels and registers are reset #1 MIER Module Interrupt Enable Register 0x10 32 read-write n 0x0 0x0 TIE0 Channel 0 Timer Interrupt Enable 0 1 read-write 0 Interrupt generation is disabled #0 1 Interrupt generation is enabled #1 TIE1 Channel 1 Timer Interrupt Enable 1 1 read-write 0 Interrupt generation is disabled #0 1 Interrupt generation is enabled #1 TIE2 Channel 2 Timer Interrupt Enable 2 1 read-write 0 Interrupt generation is disabled #0 1 Interrupt generation is enabled #1 TIE3 Channel 3 Timer Interrupt Enable 3 1 read-write 0 Interrupt generation is disabled #0 1 Interrupt generation is enabled #1 MSR Module Status Register 0xC 32 read-write n 0x0 0x0 TIF0 Channel 0 Timer Interrupt Flag 0 1 read-write 0 Timer has not timed out #0 1 Timeout has occurred #1 TIF1 Channel 1 Timer Interrupt Flag 1 1 read-write 0 Timer has not timed out #0 1 Timeout has occurred #1 TIF2 Channel 2 Timer Interrupt Flag 2 1 read-write 0 Timer has not timed out #0 1 Timeout has occurred #1 TIF3 Channel 3 Timer Interrupt Flag 3 1 read-write 0 Timer has not timed out #0 1 Timeout has occurred #1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 CHANNEL Number of Timer Channels 0 8 read-only EXT_TRIG Number of External Trigger Inputs 8 8 read-only SETTEN Set Timer Enable Register 0x14 32 read-write n 0x0 0x0 SET_T_EN_0 Set Timer 0 Enable 0 1 read-write 0 No effect #0 1 Enables the Timer Channel 0 #1 SET_T_EN_1 Set Timer 1 Enable 1 1 read-write 0 No Effect #0 1 Enables the Timer Channel 1 #1 SET_T_EN_2 Set Timer 2 Enable 2 1 read-write 0 No Effect #0 1 Enables the Timer Channel 2 #1 SET_T_EN_3 Set Timer 3 Enable 3 1 read-write 0 No effect #0 1 Enables the Timer Channel 3 #1 TCTRL0 Timer Control Register 0x50 32 read-write n 0x0 0x0 CHAIN Chain Channel 1 1 read-write 0 Channel Chaining is disabled. Channel Timer runs independently. #0 1 Channel Chaining is enabled. Timer decrements on previous channel's timeout #1 MODE Timer Operation Mode 2 2 read-write 00 32-bit Periodic Counter #00 01 Dual 16-bit Periodic Counter #01 10 32-bit Trigger Accumulator #10 11 32-bit Trigger Input Capture #11 TRG_SEL Trigger Select 24 4 read-write 0 Timer channel 0 trigger source is selected #0000 1 Timer channel 1 trigger source is selected #0001 10 Timer channel 2 trigger source is selected #0010 TRG_SRC Trigger Source 23 1 read-write 0 Trigger source selected in external #0 1 Trigger source selected is the internal trigger #1 TROT Timer Reload On Trigger 18 1 read-write 0 Timer will not reload on selected trigger #0 1 Timer will reload on selected trigger #1 TSOI Timer Stop On Interrupt 17 1 read-write 0 Timer does not stop after timeout #0 1 Timer will stop after timeout and will restart after rising edge on the T_EN bit is detected (i.e. timer channel is disabled and then enabled) #1 TSOT Timer Start On Trigger 16 1 read-write 0 Timer starts to decrement immediately based on restart condition (controlled by TSOI bit) #0 1 Timer starts to decrement when rising edge on selected trigger is detected #1 T_EN Timer Enable 0 1 read-write 0 Timer Channel is disabled #0 1 Timer Channel is enabled #1 TCTRL1 Timer Control Register 0x88 32 read-write n 0x0 0x0 CHAIN Chain Channel 1 1 read-write 0 Channel Chaining is disabled. Channel Timer runs independently. #0 1 Channel Chaining is enabled. Timer decrements on previous channel's timeout #1 MODE Timer Operation Mode 2 2 read-write 00 32-bit Periodic Counter #00 01 Dual 16-bit Periodic Counter #01 10 32-bit Trigger Accumulator #10 11 32-bit Trigger Input Capture #11 TRG_SEL Trigger Select 24 4 read-write 0 Timer channel 0 trigger source is selected #0000 1 Timer channel 1 trigger source is selected #0001 10 Timer channel 2 trigger source is selected #0010 TRG_SRC Trigger Source 23 1 read-write 0 Trigger source selected in external #0 1 Trigger source selected is the internal trigger #1 TROT Timer Reload On Trigger 18 1 read-write 0 Timer will not reload on selected trigger #0 1 Timer will reload on selected trigger #1 TSOI Timer Stop On Interrupt 17 1 read-write 0 Timer does not stop after timeout #0 1 Timer will stop after timeout and will restart after rising edge on the T_EN bit is detected (i.e. timer channel is disabled and then enabled) #1 TSOT Timer Start On Trigger 16 1 read-write 0 Timer starts to decrement immediately based on restart condition (controlled by TSOI bit) #0 1 Timer starts to decrement when rising edge on selected trigger is detected #1 T_EN Timer Enable 0 1 read-write 0 Timer Channel is disabled #0 1 Timer Channel is enabled #1 TCTRL2 Timer Control Register 0xD0 32 read-write n 0x0 0x0 CHAIN Chain Channel 1 1 read-write 0 Channel Chaining is disabled. Channel Timer runs independently. #0 1 Channel Chaining is enabled. Timer decrements on previous channel's timeout #1 MODE Timer Operation Mode 2 2 read-write 00 32-bit Periodic Counter #00 01 Dual 16-bit Periodic Counter #01 10 32-bit Trigger Accumulator #10 11 32-bit Trigger Input Capture #11 TRG_SEL Trigger Select 24 4 read-write 0 Timer channel 0 trigger source is selected #0000 1 Timer channel 1 trigger source is selected #0001 10 Timer channel 2 trigger source is selected #0010 TRG_SRC Trigger Source 23 1 read-write 0 Trigger source selected in external #0 1 Trigger source selected is the internal trigger #1 TROT Timer Reload On Trigger 18 1 read-write 0 Timer will not reload on selected trigger #0 1 Timer will reload on selected trigger #1 TSOI Timer Stop On Interrupt 17 1 read-write 0 Timer does not stop after timeout #0 1 Timer will stop after timeout and will restart after rising edge on the T_EN bit is detected (i.e. timer channel is disabled and then enabled) #1 TSOT Timer Start On Trigger 16 1 read-write 0 Timer starts to decrement immediately based on restart condition (controlled by TSOI bit) #0 1 Timer starts to decrement when rising edge on selected trigger is detected #1 T_EN Timer Enable 0 1 read-write 0 Timer Channel is disabled #0 1 Timer Channel is enabled #1 TCTRL3 Timer Control Register 0x128 32 read-write n 0x0 0x0 CHAIN Chain Channel 1 1 read-write 0 Channel Chaining is disabled. Channel Timer runs independently. #0 1 Channel Chaining is enabled. Timer decrements on previous channel's timeout #1 MODE Timer Operation Mode 2 2 read-write 00 32-bit Periodic Counter #00 01 Dual 16-bit Periodic Counter #01 10 32-bit Trigger Accumulator #10 11 32-bit Trigger Input Capture #11 TRG_SEL Trigger Select 24 4 read-write 0 Timer channel 0 trigger source is selected #0000 1 Timer channel 1 trigger source is selected #0001 10 Timer channel 2 trigger source is selected #0010 TRG_SRC Trigger Source 23 1 read-write 0 Trigger source selected in external #0 1 Trigger source selected is the internal trigger #1 TROT Timer Reload On Trigger 18 1 read-write 0 Timer will not reload on selected trigger #0 1 Timer will reload on selected trigger #1 TSOI Timer Stop On Interrupt 17 1 read-write 0 Timer does not stop after timeout #0 1 Timer will stop after timeout and will restart after rising edge on the T_EN bit is detected (i.e. timer channel is disabled and then enabled) #1 TSOT Timer Start On Trigger 16 1 read-write 0 Timer starts to decrement immediately based on restart condition (controlled by TSOI bit) #0 1 Timer starts to decrement when rising edge on selected trigger is detected #1 T_EN Timer Enable 0 1 read-write 0 Timer Channel is disabled #0 1 Timer Channel is enabled #1 TVAL0 Timer Value Register 0x40 32 read-write n 0x0 0x0 TMR_VAL Timer Value 0 32 read-write 0 Invalid load value in compare modes #0 TVAL1 Timer Value Register 0x70 32 read-write n 0x0 0x0 TMR_VAL Timer Value 0 32 read-write 0 Invalid load value in compare modes #0 TVAL2 Timer Value Register 0xB0 32 read-write n 0x0 0x0 TMR_VAL Timer Value 0 32 read-write 0 Invalid load value in compare modes #0 TVAL3 Timer Value Register 0x100 32 read-write n 0x0 0x0 TMR_VAL Timer Value 0 32 read-write 0 Invalid load value in compare modes #0 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Number 0 16 read-only MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only LPSPI0 The LPSPI Memory Map/Register Definition can be found here. LPSPI 0x0 0x0 0x78 registers n LPSPI0 10 CCR Clock Configuration Register 0x40 32 read-write n 0x0 0x0 DBT Delay Between Transfers 8 8 read-write PCSSCK PCS to SCK Delay 16 8 read-write SCKDIV SCK Divider 0 8 read-write SCKPCS SCK to PCS Delay 24 8 read-write CFGR0 Configuration Register 0 0x20 32 read-write n 0x0 0x0 CIRFIFO Circular FIFO Enable 8 1 read-write 0 Circular FIFO is disabled. #0 1 Circular FIFO is enabled. #1 HREN Host Request Enable 0 1 read-write 0 Host request is disabled. #0 1 Host request is enabled. #1 HRPOL Host Request Polarity 1 1 read-write 0 Active low. #0 1 Active high. #1 HRSEL Host Request Select 2 1 read-write 0 Host request input is pin LPSPI_HREQ. #0 1 Host request input is input trigger. #1 RDMO Receive Data Match Only 9 1 read-write 0 Received data is stored in the receive FIFO as normal. #0 1 Received data is discarded unless the DMF is set. #1 CFGR1 Configuration Register 1 0x24 32 read-write n 0x0 0x0 AUTOPCS Automatic PCS 2 1 read-write 0 Automatic PCS generation disabled. #0 1 Automatic PCS generation enabled. #1 MASTER Master Mode 0 1 read-write 0 Slave mode. #0 1 Master mode. #1 MATCFG Match Configuration 16 3 read-write 000 Match disabled. #000 010 Match enabled (1st data word equals MATCH0 OR MATCH1). #010 011 Match enabled (any data word equals MATCH0 OR MATCH1). #011 100 Match enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1). #100 101 Match enabled (any data word equals MATCH0 AND next data word equals MATCH1) #101 110 Match enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) #110 111 Match enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1). #111 NOSTALL No Stall 3 1 read-write 0 Transfers will stall when transmit FIFO is empty or receive FIFO is full. #0 1 Transfers will not stall, allowing transmit FIFO underrun or receive FIFO overrun to occur. #1 OUTCFG Output Config 26 1 read-write 0 Output data retains last value when chip select is negated. #0 1 Output data is tristated when chip select is negated. #1 PCSCFG Peripheral Chip Select Configuration 27 1 read-write 0 PCS[3:2] are enabled. #0 1 PCS[3:2] are disabled. #1 PCSPOL Peripheral Chip Select Polarity 8 4 read-write 0 The PCSx is active low. #0000 1 The PCSx is active high. #0001 PINCFG Pin Configuration 24 2 read-write 00 SIN is used for input data and SOUT for output data. #00 01 SIN is used for both input and output data. #01 10 SOUT is used for both input and output data. #10 11 SOUT is used for input data and SIN for output data. #11 SAMPLE Sample Point 1 1 read-write 0 Input data sampled on SCK edge. #0 1 Input data sampled on delayed SCK edge. #1 CR Control Register 0x10 32 read-write n 0x0 0x0 DBGEN Debug Enable 3 1 read-write 0 Module is disabled in debug mode. #0 1 Module is enabled in debug mode. #1 DOZEN Doze mode enable 2 1 read-write 0 Module is enabled in Doze mode. #0 1 Module is disabled in Doze mode. #1 MEN Module Enable 0 1 read-write 0 Module is disabled. #0 1 Module is enabled. #1 RRF Reset Receive FIFO 9 1 write-only 0 No effect. #0 1 Receive FIFO is reset. #1 RST Software Reset 1 1 read-write 0 Master logic is not reset. #0 1 Master logic is reset. #1 RTF Reset Transmit FIFO 8 1 write-only 0 No effect. #0 1 Transmit FIFO is reset. #1 DER DMA Enable Register 0x1C 32 read-write n 0x0 0x0 RDDE Receive Data DMA Enable 1 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 TDDE Transmit Data DMA Enable 0 1 read-write 0 DMA request disabled. #0 1 DMA request enabled #1 DMR0 Data Match Register 0 0x30 32 read-write n 0x0 0x0 MATCH0 Match 0 Value 0 32 read-write DMR1 Data Match Register 1 0x34 32 read-write n 0x0 0x0 MATCH1 Match 1 Value 0 32 read-write FCR FIFO Control Register 0x58 32 read-write n 0x0 0x0 RXWATER Receive FIFO Watermark 16 8 read-write TXWATER Transmit FIFO Watermark 0 8 read-write FSR FIFO Status Register 0x5C 32 read-only n 0x0 0x0 RXCOUNT Receive FIFO Count 16 8 read-only TXCOUNT Transmit FIFO Count 0 8 read-only IER Interrupt Enable Register 0x18 32 read-write n 0x0 0x0 DMIE Data Match Interrupt Enable 13 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 FCIE Frame Complete Interrupt Enable 9 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 RDIE Receive Data Interrupt Enable 1 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 REIE Receive Error Interrupt Enable 12 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 TCIE Transfer Complete Interrupt Enable 10 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 TDIE Transmit Data Interrupt Enable 0 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled #1 TEIE Transmit Error Interrupt Enable 11 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 WCIE Word Complete Interrupt Enable 8 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 RXFIFO Receive FIFO Size 8 8 read-only TXFIFO Transmit FIFO Size 0 8 read-only RDR Receive Data Register 0x74 32 read-only n 0x0 0x0 DATA Receive Data 0 32 read-only RSR Receive Status Register 0x70 32 read-only n 0x0 0x0 RXEMPTY RX FIFO Empty 1 1 read-only 0 RX FIFO is not empty. #0 1 RX FIFO is empty. #1 SOF Start Of Frame 0 1 read-only 0 Subsequent data word received after LPSPI_PCS assertion. #0 1 First data word received after LPSPI_PCS assertion. #1 SR Status Register 0x14 32 read-write n 0x0 0x0 DMF Data Match Flag 13 1 read-write 0 Have not received matching data. #0 1 Have received matching data. #1 FCF Frame Complete Flag 9 1 read-write 0 Frame transfer has not completed. #0 1 Frame transfer has completed. #1 MBF Module Busy Flag 24 1 read-only 0 LPSPI is idle. #0 1 LPSPI is busy. #1 RDF Receive Data Flag 1 1 read-only 0 Receive Data is not ready. #0 1 Receive data is ready. #1 REF Receive Error Flag 12 1 read-write 0 Receive FIFO has not overflowed. #0 1 Receive FIFO has overflowed. #1 TCF Transfer Complete Flag 10 1 read-write 0 All transfers have not completed. #0 1 All transfers have completed. #1 TDF Transmit Data Flag 0 1 read-only 0 Transmit data not requested. #0 1 Transmit data is requested. #1 TEF Transmit Error Flag 11 1 read-write 0 Transmit FIFO underrun has not occurred. #0 1 Transmit FIFO underrun has occurred #1 WCF Word Complete Flag 8 1 read-write 0 Transfer word not completed. #0 1 Transfer word completed. #1 TCR Transmit Command Register 0x60 32 read-write n 0x0 0x0 BYSW Byte Swap 22 1 read-write 0 Byte swap disabled. #0 1 Byte swap enabled. #1 CONT Continuous Transfer 21 1 read-write 0 Continuous transfer disabled. #0 1 Continuous transfer enabled. #1 CONTC Continuing Command 20 1 read-write 0 Command word for start of new transfer. #0 1 Command word for continuing transfer. #1 CPHA Clock Phase 30 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 31 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FRAMESZ Frame Size 0 12 read-write LSBF LSB First 23 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 PCS Peripheral Chip Select 24 2 read-write 00 Transfer using LPSPI_PCS[0] #00 01 Transfer using LPSPI_PCS[1] #01 10 Transfer using LPSPI_PCS[2] #10 11 Transfer using LPSPI_PCS[3] #11 PRESCALE Prescaler Value 27 3 read-write 000 Divide by 1. #000 001 Divide by 2. #001 010 Divide by 4. #010 011 Divide by 8. #011 100 Divide by 16. #100 101 Divide by 32. #101 110 Divide by 64. #110 111 Divide by 128. #111 RXMSK Receive Data Mask 19 1 read-write 0 Normal transfer. #0 1 Receive data is masked. #1 TXMSK Transmit Data Mask 18 1 read-write 00 Normal transfer. #0 01 Mask transmit data. #1 WIDTH Transfer Width 16 2 read-write 00 Single bit transfer. #00 01 Two bit transfer. #01 10 Four bit transfer. #10 TDR Transmit Data Register 0x64 32 write-only n 0x0 0x0 DATA Transmit Data 0 32 write-only VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Module Identification Number 0 16 read-only 100 Standard feature set supporting 32-bit shift register. #100 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only LPSPI1 The LPSPI Memory Map/Register Definition can be found here. LPSPI 0x0 0x0 0x78 registers n LPSPI1 11 CCR Clock Configuration Register 0x40 32 read-write n 0x0 0x0 DBT Delay Between Transfers 8 8 read-write PCSSCK PCS to SCK Delay 16 8 read-write SCKDIV SCK Divider 0 8 read-write SCKPCS SCK to PCS Delay 24 8 read-write CFGR0 Configuration Register 0 0x20 32 read-write n 0x0 0x0 CIRFIFO Circular FIFO Enable 8 1 read-write 0 Circular FIFO is disabled. #0 1 Circular FIFO is enabled. #1 HREN Host Request Enable 0 1 read-write 0 Host request is disabled. #0 1 Host request is enabled. #1 HRPOL Host Request Polarity 1 1 read-write 0 Active low. #0 1 Active high. #1 HRSEL Host Request Select 2 1 read-write 0 Host request input is pin LPSPI_HREQ. #0 1 Host request input is input trigger. #1 RDMO Receive Data Match Only 9 1 read-write 0 Received data is stored in the receive FIFO as normal. #0 1 Received data is discarded unless the DMF is set. #1 CFGR1 Configuration Register 1 0x24 32 read-write n 0x0 0x0 AUTOPCS Automatic PCS 2 1 read-write 0 Automatic PCS generation disabled. #0 1 Automatic PCS generation enabled. #1 MASTER Master Mode 0 1 read-write 0 Slave mode. #0 1 Master mode. #1 MATCFG Match Configuration 16 3 read-write 000 Match disabled. #000 010 Match enabled (1st data word equals MATCH0 OR MATCH1). #010 011 Match enabled (any data word equals MATCH0 OR MATCH1). #011 100 Match enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1). #100 101 Match enabled (any data word equals MATCH0 AND next data word equals MATCH1) #101 110 Match enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) #110 111 Match enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1). #111 NOSTALL No Stall 3 1 read-write 0 Transfers will stall when transmit FIFO is empty or receive FIFO is full. #0 1 Transfers will not stall, allowing transmit FIFO underrun or receive FIFO overrun to occur. #1 OUTCFG Output Config 26 1 read-write 0 Output data retains last value when chip select is negated. #0 1 Output data is tristated when chip select is negated. #1 PCSCFG Peripheral Chip Select Configuration 27 1 read-write 0 PCS[3:2] are enabled. #0 1 PCS[3:2] are disabled. #1 PCSPOL Peripheral Chip Select Polarity 8 4 read-write 0 The PCSx is active low. #0000 1 The PCSx is active high. #0001 PINCFG Pin Configuration 24 2 read-write 00 SIN is used for input data and SOUT for output data. #00 01 SIN is used for both input and output data. #01 10 SOUT is used for both input and output data. #10 11 SOUT is used for input data and SIN for output data. #11 SAMPLE Sample Point 1 1 read-write 0 Input data sampled on SCK edge. #0 1 Input data sampled on delayed SCK edge. #1 CR Control Register 0x10 32 read-write n 0x0 0x0 DBGEN Debug Enable 3 1 read-write 0 Module is disabled in debug mode. #0 1 Module is enabled in debug mode. #1 DOZEN Doze mode enable 2 1 read-write 0 Module is enabled in Doze mode. #0 1 Module is disabled in Doze mode. #1 MEN Module Enable 0 1 read-write 0 Module is disabled. #0 1 Module is enabled. #1 RRF Reset Receive FIFO 9 1 write-only 0 No effect. #0 1 Receive FIFO is reset. #1 RST Software Reset 1 1 read-write 0 Master logic is not reset. #0 1 Master logic is reset. #1 RTF Reset Transmit FIFO 8 1 write-only 0 No effect. #0 1 Transmit FIFO is reset. #1 DER DMA Enable Register 0x1C 32 read-write n 0x0 0x0 RDDE Receive Data DMA Enable 1 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 TDDE Transmit Data DMA Enable 0 1 read-write 0 DMA request disabled. #0 1 DMA request enabled #1 DMR0 Data Match Register 0 0x30 32 read-write n 0x0 0x0 MATCH0 Match 0 Value 0 32 read-write DMR1 Data Match Register 1 0x34 32 read-write n 0x0 0x0 MATCH1 Match 1 Value 0 32 read-write FCR FIFO Control Register 0x58 32 read-write n 0x0 0x0 RXWATER Receive FIFO Watermark 16 8 read-write TXWATER Transmit FIFO Watermark 0 8 read-write FSR FIFO Status Register 0x5C 32 read-only n 0x0 0x0 RXCOUNT Receive FIFO Count 16 8 read-only TXCOUNT Transmit FIFO Count 0 8 read-only IER Interrupt Enable Register 0x18 32 read-write n 0x0 0x0 DMIE Data Match Interrupt Enable 13 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 FCIE Frame Complete Interrupt Enable 9 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 RDIE Receive Data Interrupt Enable 1 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 REIE Receive Error Interrupt Enable 12 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 TCIE Transfer Complete Interrupt Enable 10 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 TDIE Transmit Data Interrupt Enable 0 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled #1 TEIE Transmit Error Interrupt Enable 11 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 WCIE Word Complete Interrupt Enable 8 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 RXFIFO Receive FIFO Size 8 8 read-only TXFIFO Transmit FIFO Size 0 8 read-only RDR Receive Data Register 0x74 32 read-only n 0x0 0x0 DATA Receive Data 0 32 read-only RSR Receive Status Register 0x70 32 read-only n 0x0 0x0 RXEMPTY RX FIFO Empty 1 1 read-only 0 RX FIFO is not empty. #0 1 RX FIFO is empty. #1 SOF Start Of Frame 0 1 read-only 0 Subsequent data word received after LPSPI_PCS assertion. #0 1 First data word received after LPSPI_PCS assertion. #1 SR Status Register 0x14 32 read-write n 0x0 0x0 DMF Data Match Flag 13 1 read-write 0 Have not received matching data. #0 1 Have received matching data. #1 FCF Frame Complete Flag 9 1 read-write 0 Frame transfer has not completed. #0 1 Frame transfer has completed. #1 MBF Module Busy Flag 24 1 read-only 0 LPSPI is idle. #0 1 LPSPI is busy. #1 RDF Receive Data Flag 1 1 read-only 0 Receive Data is not ready. #0 1 Receive data is ready. #1 REF Receive Error Flag 12 1 read-write 0 Receive FIFO has not overflowed. #0 1 Receive FIFO has overflowed. #1 TCF Transfer Complete Flag 10 1 read-write 0 All transfers have not completed. #0 1 All transfers have completed. #1 TDF Transmit Data Flag 0 1 read-only 0 Transmit data not requested. #0 1 Transmit data is requested. #1 TEF Transmit Error Flag 11 1 read-write 0 Transmit FIFO underrun has not occurred. #0 1 Transmit FIFO underrun has occurred #1 WCF Word Complete Flag 8 1 read-write 0 Transfer word not completed. #0 1 Transfer word completed. #1 TCR Transmit Command Register 0x60 32 read-write n 0x0 0x0 BYSW Byte Swap 22 1 read-write 0 Byte swap disabled. #0 1 Byte swap enabled. #1 CONT Continuous Transfer 21 1 read-write 0 Continuous transfer disabled. #0 1 Continuous transfer enabled. #1 CONTC Continuing Command 20 1 read-write 0 Command word for start of new transfer. #0 1 Command word for continuing transfer. #1 CPHA Clock Phase 30 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 31 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FRAMESZ Frame Size 0 12 read-write LSBF LSB First 23 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 PCS Peripheral Chip Select 24 2 read-write 00 Transfer using LPSPI_PCS[0] #00 01 Transfer using LPSPI_PCS[1] #01 10 Transfer using LPSPI_PCS[2] #10 11 Transfer using LPSPI_PCS[3] #11 PRESCALE Prescaler Value 27 3 read-write 000 Divide by 1. #000 001 Divide by 2. #001 010 Divide by 4. #010 011 Divide by 8. #011 100 Divide by 16. #100 101 Divide by 32. #101 110 Divide by 64. #110 111 Divide by 128. #111 RXMSK Receive Data Mask 19 1 read-write 0 Normal transfer. #0 1 Receive data is masked. #1 TXMSK Transmit Data Mask 18 1 read-write 00 Normal transfer. #0 01 Mask transmit data. #1 WIDTH Transfer Width 16 2 read-write 00 Single bit transfer. #00 01 Two bit transfer. #01 10 Four bit transfer. #10 TDR Transmit Data Register 0x64 32 write-only n 0x0 0x0 DATA Transmit Data 0 32 write-only VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Module Identification Number 0 16 read-only 100 Standard feature set supporting 32-bit shift register. #100 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only LPSPI2 The LPSPI Memory Map/Register Definition can be found here. LPSPI 0x0 0x0 0x78 registers n LPSPI2 36 CCR Clock Configuration Register 0x40 32 read-write n 0x0 0x0 DBT Delay Between Transfers 8 8 read-write PCSSCK PCS to SCK Delay 16 8 read-write SCKDIV SCK Divider 0 8 read-write SCKPCS SCK to PCS Delay 24 8 read-write CFGR0 Configuration Register 0 0x20 32 read-write n 0x0 0x0 CIRFIFO Circular FIFO Enable 8 1 read-write 0 Circular FIFO is disabled. #0 1 Circular FIFO is enabled. #1 HREN Host Request Enable 0 1 read-write 0 Host request is disabled. #0 1 Host request is enabled. #1 HRPOL Host Request Polarity 1 1 read-write 0 Active low. #0 1 Active high. #1 HRSEL Host Request Select 2 1 read-write 0 Host request input is pin LPSPI_HREQ. #0 1 Host request input is input trigger. #1 RDMO Receive Data Match Only 9 1 read-write 0 Received data is stored in the receive FIFO as normal. #0 1 Received data is discarded unless the DMF is set. #1 CFGR1 Configuration Register 1 0x24 32 read-write n 0x0 0x0 AUTOPCS Automatic PCS 2 1 read-write 0 Automatic PCS generation disabled. #0 1 Automatic PCS generation enabled. #1 MASTER Master Mode 0 1 read-write 0 Slave mode. #0 1 Master mode. #1 MATCFG Match Configuration 16 3 read-write 000 Match disabled. #000 010 Match enabled (1st data word equals MATCH0 OR MATCH1). #010 011 Match enabled (any data word equals MATCH0 OR MATCH1). #011 100 Match enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1). #100 101 Match enabled (any data word equals MATCH0 AND next data word equals MATCH1) #101 110 Match enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) #110 111 Match enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1). #111 NOSTALL No Stall 3 1 read-write 0 Transfers will stall when transmit FIFO is empty or receive FIFO is full. #0 1 Transfers will not stall, allowing transmit FIFO underrun or receive FIFO overrun to occur. #1 OUTCFG Output Config 26 1 read-write 0 Output data retains last value when chip select is negated. #0 1 Output data is tristated when chip select is negated. #1 PCSCFG Peripheral Chip Select Configuration 27 1 read-write 0 PCS[3:2] are enabled. #0 1 PCS[3:2] are disabled. #1 PCSPOL Peripheral Chip Select Polarity 8 4 read-write 0 The PCSx is active low. #0000 1 The PCSx is active high. #0001 PINCFG Pin Configuration 24 2 read-write 00 SIN is used for input data and SOUT for output data. #00 01 SIN is used for both input and output data. #01 10 SOUT is used for both input and output data. #10 11 SOUT is used for input data and SIN for output data. #11 SAMPLE Sample Point 1 1 read-write 0 Input data sampled on SCK edge. #0 1 Input data sampled on delayed SCK edge. #1 CR Control Register 0x10 32 read-write n 0x0 0x0 DBGEN Debug Enable 3 1 read-write 0 Module is disabled in debug mode. #0 1 Module is enabled in debug mode. #1 DOZEN Doze mode enable 2 1 read-write 0 Module is enabled in Doze mode. #0 1 Module is disabled in Doze mode. #1 MEN Module Enable 0 1 read-write 0 Module is disabled. #0 1 Module is enabled. #1 RRF Reset Receive FIFO 9 1 write-only 0 No effect. #0 1 Receive FIFO is reset. #1 RST Software Reset 1 1 read-write 0 Master logic is not reset. #0 1 Master logic is reset. #1 RTF Reset Transmit FIFO 8 1 write-only 0 No effect. #0 1 Transmit FIFO is reset. #1 DER DMA Enable Register 0x1C 32 read-write n 0x0 0x0 RDDE Receive Data DMA Enable 1 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 TDDE Transmit Data DMA Enable 0 1 read-write 0 DMA request disabled. #0 1 DMA request enabled #1 DMR0 Data Match Register 0 0x30 32 read-write n 0x0 0x0 MATCH0 Match 0 Value 0 32 read-write DMR1 Data Match Register 1 0x34 32 read-write n 0x0 0x0 MATCH1 Match 1 Value 0 32 read-write FCR FIFO Control Register 0x58 32 read-write n 0x0 0x0 RXWATER Receive FIFO Watermark 16 8 read-write TXWATER Transmit FIFO Watermark 0 8 read-write FSR FIFO Status Register 0x5C 32 read-only n 0x0 0x0 RXCOUNT Receive FIFO Count 16 8 read-only TXCOUNT Transmit FIFO Count 0 8 read-only IER Interrupt Enable Register 0x18 32 read-write n 0x0 0x0 DMIE Data Match Interrupt Enable 13 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 FCIE Frame Complete Interrupt Enable 9 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 RDIE Receive Data Interrupt Enable 1 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 REIE Receive Error Interrupt Enable 12 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 TCIE Transfer Complete Interrupt Enable 10 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 TDIE Transmit Data Interrupt Enable 0 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled #1 TEIE Transmit Error Interrupt Enable 11 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 WCIE Word Complete Interrupt Enable 8 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 RXFIFO Receive FIFO Size 8 8 read-only TXFIFO Transmit FIFO Size 0 8 read-only RDR Receive Data Register 0x74 32 read-only n 0x0 0x0 DATA Receive Data 0 32 read-only RSR Receive Status Register 0x70 32 read-only n 0x0 0x0 RXEMPTY RX FIFO Empty 1 1 read-only 0 RX FIFO is not empty. #0 1 RX FIFO is empty. #1 SOF Start Of Frame 0 1 read-only 0 Subsequent data word received after LPSPI_PCS assertion. #0 1 First data word received after LPSPI_PCS assertion. #1 SR Status Register 0x14 32 read-write n 0x0 0x0 DMF Data Match Flag 13 1 read-write 0 Have not received matching data. #0 1 Have received matching data. #1 FCF Frame Complete Flag 9 1 read-write 0 Frame transfer has not completed. #0 1 Frame transfer has completed. #1 MBF Module Busy Flag 24 1 read-only 0 LPSPI is idle. #0 1 LPSPI is busy. #1 RDF Receive Data Flag 1 1 read-only 0 Receive Data is not ready. #0 1 Receive data is ready. #1 REF Receive Error Flag 12 1 read-write 0 Receive FIFO has not overflowed. #0 1 Receive FIFO has overflowed. #1 TCF Transfer Complete Flag 10 1 read-write 0 All transfers have not completed. #0 1 All transfers have completed. #1 TDF Transmit Data Flag 0 1 read-only 0 Transmit data not requested. #0 1 Transmit data is requested. #1 TEF Transmit Error Flag 11 1 read-write 0 Transmit FIFO underrun has not occurred. #0 1 Transmit FIFO underrun has occurred #1 WCF Word Complete Flag 8 1 read-write 0 Transfer word not completed. #0 1 Transfer word completed. #1 TCR Transmit Command Register 0x60 32 read-write n 0x0 0x0 BYSW Byte Swap 22 1 read-write 0 Byte swap disabled. #0 1 Byte swap enabled. #1 CONT Continuous Transfer 21 1 read-write 0 Continuous transfer disabled. #0 1 Continuous transfer enabled. #1 CONTC Continuing Command 20 1 read-write 0 Command word for start of new transfer. #0 1 Command word for continuing transfer. #1 CPHA Clock Phase 30 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 31 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FRAMESZ Frame Size 0 12 read-write LSBF LSB First 23 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 PCS Peripheral Chip Select 24 2 read-write 00 Transfer using LPSPI_PCS[0] #00 01 Transfer using LPSPI_PCS[1] #01 10 Transfer using LPSPI_PCS[2] #10 11 Transfer using LPSPI_PCS[3] #11 PRESCALE Prescaler Value 27 3 read-write 000 Divide by 1. #000 001 Divide by 2. #001 010 Divide by 4. #010 011 Divide by 8. #011 100 Divide by 16. #100 101 Divide by 32. #101 110 Divide by 64. #110 111 Divide by 128. #111 RXMSK Receive Data Mask 19 1 read-write 0 Normal transfer. #0 1 Receive data is masked. #1 TXMSK Transmit Data Mask 18 1 read-write 00 Normal transfer. #0 01 Mask transmit data. #1 WIDTH Transfer Width 16 2 read-write 00 Single bit transfer. #00 01 Two bit transfer. #01 10 Four bit transfer. #10 TDR Transmit Data Register 0x64 32 write-only n 0x0 0x0 DATA Transmit Data 0 32 write-only VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Module Identification Number 0 16 read-only 100 Standard feature set supporting 32-bit shift register. #100 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only LPTMR0 Low Power Timer LPTMR 0x0 0x0 0x10 registers n LPTMR0 26 CMR Low Power Timer Compare Register 0x8 32 read-write n 0x0 0x0 COMPARE Compare Value 0 16 read-write CNR Low Power Timer Counter Register 0xC 32 read-write n 0x0 0x0 COUNTER Counter Value 0 16 read-write CSR Low Power Timer Control Status Register 0x0 32 read-write n 0x0 0x0 TCF Timer Compare Flag 7 1 read-write 0 The value of CNR is not equal to CMR and increments. #0 1 The value of CNR is equal to CMR and increments. #1 TDRE Timer DMA Request Enable 8 1 read-write 0 Timer DMA Request disabled. #0 1 Timer DMA Request enabled. #1 TEN Timer Enable 0 1 read-write 0 LPTMR is disabled and internal logic is reset. #0 1 LPTMR is enabled. #1 TFC Timer Free-Running Counter 2 1 read-write 0 CNR is reset whenever TCF is set. #0 1 CNR is reset on overflow. #1 TIE Timer Interrupt Enable 6 1 read-write 0 Timer interrupt disabled. #0 1 Timer interrupt enabled. #1 TMS Timer Mode Select 1 1 read-write 0 Time Counter mode. #0 1 Pulse Counter mode. #1 TPP Timer Pin Polarity 3 1 read-write 0 Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. #0 1 Pulse Counter input source is active-low, and the CNR will increment on the falling-edge. #1 TPS Timer Pin Select 4 2 read-write 00 Pulse counter input 0 is selected. #00 01 Pulse counter input 1 is selected. #01 10 Pulse counter input 2 is selected. #10 11 Pulse counter input 3 is selected. #11 PSR Low Power Timer Prescale Register 0x4 32 read-write n 0x0 0x0 PBYP Prescaler Bypass 2 1 read-write 0 Prescaler/glitch filter is enabled. #0 1 Prescaler/glitch filter is bypassed. #1 PCS Prescaler Clock Select 0 2 read-write 00 Prescaler/glitch filter clock 0 selected. #00 01 Prescaler/glitch filter clock 1 selected. #01 10 Prescaler/glitch filter clock 2 selected. #10 11 Prescaler/glitch filter clock 3 selected. #11 PRESCALE Prescale Value 3 4 read-write 0000 Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. #0000 0001 Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. #0001 0010 Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. #0010 0011 Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. #0011 0100 Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. #0100 0101 Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. #0101 0110 Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. #0110 0111 Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. #0111 1000 Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. #1000 1001 Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. #1001 1010 Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. #1010 1011 Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. #1011 1100 Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. #1100 1101 Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. #1101 1110 Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. #1110 1111 Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. #1111 LPTMR1 Low Power Timer LPTMR 0x0 0x0 0x10 registers n LPTMR1 32 CMR Low Power Timer Compare Register 0x8 32 read-write n 0x0 0x0 COMPARE Compare Value 0 16 read-write CNR Low Power Timer Counter Register 0xC 32 read-write n 0x0 0x0 COUNTER Counter Value 0 16 read-write CSR Low Power Timer Control Status Register 0x0 32 read-write n 0x0 0x0 TCF Timer Compare Flag 7 1 read-write 0 The value of CNR is not equal to CMR and increments. #0 1 The value of CNR is equal to CMR and increments. #1 TDRE Timer DMA Request Enable 8 1 read-write 0 Timer DMA Request disabled. #0 1 Timer DMA Request enabled. #1 TEN Timer Enable 0 1 read-write 0 LPTMR is disabled and internal logic is reset. #0 1 LPTMR is enabled. #1 TFC Timer Free-Running Counter 2 1 read-write 0 CNR is reset whenever TCF is set. #0 1 CNR is reset on overflow. #1 TIE Timer Interrupt Enable 6 1 read-write 0 Timer interrupt disabled. #0 1 Timer interrupt enabled. #1 TMS Timer Mode Select 1 1 read-write 0 Time Counter mode. #0 1 Pulse Counter mode. #1 TPP Timer Pin Polarity 3 1 read-write 0 Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. #0 1 Pulse Counter input source is active-low, and the CNR will increment on the falling-edge. #1 TPS Timer Pin Select 4 2 read-write 00 Pulse counter input 0 is selected. #00 01 Pulse counter input 1 is selected. #01 10 Pulse counter input 2 is selected. #10 11 Pulse counter input 3 is selected. #11 PSR Low Power Timer Prescale Register 0x4 32 read-write n 0x0 0x0 PBYP Prescaler Bypass 2 1 read-write 0 Prescaler/glitch filter is enabled. #0 1 Prescaler/glitch filter is bypassed. #1 PCS Prescaler Clock Select 0 2 read-write 00 Prescaler/glitch filter clock 0 selected. #00 01 Prescaler/glitch filter clock 1 selected. #01 10 Prescaler/glitch filter clock 2 selected. #10 11 Prescaler/glitch filter clock 3 selected. #11 PRESCALE Prescale Value 3 4 read-write 0000 Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. #0000 0001 Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. #0001 0010 Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. #0010 0011 Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. #0011 0100 Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. #0100 0101 Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. #0101 0110 Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. #0110 0111 Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. #0111 1000 Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. #1000 1001 Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. #1001 1010 Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. #1010 1011 Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. #1011 1100 Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. #1100 1101 Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. #1101 1110 Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. #1110 1111 Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. #1111 LPUART0 Universal Asynchronous Receiver/Transmitter LPUART 0x0 0x0 0x30 registers n LPUART0 12 BAUD LPUART Baud Rate Register 0x10 32 read-write n 0x0 0x0 BOTHEDGE Both Edge Sampling 17 1 read-write 0 Receiver samples input data using the rising edge of the baud rate clock. #0 1 Receiver samples input data using the rising and falling edge of the baud rate clock. #1 LBKDIE LIN Break Detect Interrupt Enable 15 1 read-write 0 Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). #0 1 Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. #1 M10 10-bit Mode select 29 1 read-write 0 Receiver and transmitter use 8-bit or 9-bit data characters. #0 1 Receiver and transmitter use 10-bit data characters. #1 MAEN1 Match Address Mode Enable 1 31 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA1]. #1 MAEN2 Match Address Mode Enable 2 30 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA2]. #1 MATCFG Match Configuration 18 2 read-write 00 Address Match Wakeup #00 01 Idle Match Wakeup #01 10 Match On and Match Off #10 11 Enables RWU on Data Match and Match On/Off for transmitter CTS input #11 OSR Oversampling Ratio 24 5 read-write RDMAE Receiver Full DMA Enable 21 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 RESYNCDIS Resynchronization Disable 16 1 read-write 0 Resynchronization during received data word is supported #0 1 Resynchronization during received data word is disabled #1 RXEDGIE RX Input Active Edge Interrupt Enable 14 1 read-write 0 Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling). #0 1 Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. #1 SBNS Stop Bit Number Select 13 1 read-write 0 One stop bit. #0 1 Two stop bits. #1 SBR Baud Rate Modulo Divisor. 0 13 read-write TDMAE Transmitter DMA Enable 23 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 CTRL LPUART Control Register 0x18 32 read-write n 0x0 0x0 DOZEEN Doze Enable 6 1 read-write 0 LPUART is enabled in Doze mode. #0 1 LPUART is disabled in Doze mode. #1 FEIE Framing Error Interrupt Enable 25 1 read-write 0 FE interrupts disabled; use polling. #0 1 Hardware interrupt requested when FE is set. #1 IDLECFG Idle Configuration 8 3 read-write 000 1 idle character #000 001 2 idle characters #001 010 4 idle characters #010 011 8 idle characters #011 100 16 idle characters #100 101 32 idle characters #101 110 64 idle characters #110 111 128 idle characters #111 ILIE Idle Line Interrupt Enable 20 1 read-write 0 Hardware interrupts from IDLE disabled; use polling. #0 1 Hardware interrupt requested when IDLE flag is 1. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation - LPUART_RX and LPUART_TX use separate pins. #0 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). #1 M 9-Bit or 8-Bit Mode Select 4 1 read-write 0 Receiver and transmitter use 8-bit data characters. #0 1 Receiver and transmitter use 9-bit data characters. #1 MA1IE Match 1 Interrupt Enable 15 1 read-write 0 MA1F interrupt disabled #0 1 MA1F interrupt enabled #1 MA2IE Match 2 Interrupt Enable 14 1 read-write 0 MA2F interrupt disabled #0 1 MA2F interrupt enabled #1 NEIE Noise Error Interrupt Enable 26 1 read-write 0 NF interrupts disabled; use polling. #0 1 Hardware interrupt requested when NF is set. #1 ORIE Overrun Interrupt Enable 27 1 read-write 0 OR interrupts disabled; use polling. #0 1 Hardware interrupt requested when OR is set. #1 PE Parity Enable 1 1 read-write 0 No hardware parity generation or checking. #0 1 Parity enabled. #1 PEIE Parity Error Interrupt Enable 24 1 read-write 0 PF interrupts disabled; use polling). #0 1 Hardware interrupt requested when PF is set. #1 PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 R8T9 Receive Bit 8 / Transmit Bit 9 31 1 read-write R9T8 Receive Bit 9 / Transmit Bit 8 30 1 read-write RE Receiver Enable 18 1 read-write 0 Receiver disabled. #0 1 Receiver enabled. #1 RIE Receiver Interrupt Enable 21 1 read-write 0 Hardware interrupts from RDRF disabled; use polling. #0 1 Hardware interrupt requested when RDRF flag is 1. #1 RSRC Receiver Source Select 5 1 read-write 0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin. #0 1 Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input. #1 RWU Receiver Wakeup Control 17 1 read-write 0 Normal receiver operation. #0 1 LPUART receiver in standby waiting for wakeup condition. #1 SBK Send Break 16 1 read-write 0 Normal transmitter operation. #0 1 Queue break character(s) to be sent. #1 TCIE Transmission Complete Interrupt Enable for 22 1 read-write 0 Hardware interrupts from TC disabled; use polling. #0 1 Hardware interrupt requested when TC flag is 1. #1 TE Transmitter Enable 19 1 read-write 0 Transmitter disabled. #0 1 Transmitter enabled. #1 TIE Transmit Interrupt Enable 23 1 read-write 0 Hardware interrupts from TDRE disabled; use polling. #0 1 Hardware interrupt requested when TDRE flag is 1. #1 TXDIR LPUART_TX Pin Direction in Single-Wire Mode 29 1 read-write 0 LPUART_TX pin is an input in single-wire mode. #0 1 LPUART_TX pin is an output in single-wire mode. #1 TXINV Transmit Data Inversion 28 1 read-write 0 Transmit data not inverted. #0 1 Transmit data inverted. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Configures RWU for idle-line wakeup. #0 1 Configures RWU with address-mark wakeup. #1 DATA LPUART Data Register 0x1C 32 read-write n 0x0 0x0 FRETSC Frame Error / Transmit Special Character 13 1 read-write 0 The dataword was received without a frame error on read, transmit a normal character on write. #0 1 The dataword was received with a frame error, transmit an idle or break character on transmit. #1 IDLINE Idle Line 11 1 read-only 0 Receiver was not idle before receiving this character. #0 1 Receiver was idle before receiving this character. #1 NOISY The current received dataword contained in DATA[R9:R0] was received with noise. 15 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 PARITYE The current received dataword contained in DATA[R9:R0] was received with a parity error. 14 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 R0T0 Read receive data buffer 0 or write transmit data buffer 0. 0 1 read-write R1T1 Read receive data buffer 1 or write transmit data buffer 1. 1 1 read-write R2T2 Read receive data buffer 2 or write transmit data buffer 2. 2 1 read-write R3T3 Read receive data buffer 3 or write transmit data buffer 3. 3 1 read-write R4T4 Read receive data buffer 4 or write transmit data buffer 4. 4 1 read-write R5T5 Read receive data buffer 5 or write transmit data buffer 5. 5 1 read-write R6T6 Read receive data buffer 6 or write transmit data buffer 6. 6 1 read-write R7T7 Read receive data buffer 7 or write transmit data buffer 7. 7 1 read-write R8T8 Read receive data buffer 8 or write transmit data buffer 8. 8 1 read-write R9T9 Read receive data buffer 9 or write transmit data buffer 9. 9 1 read-write RXEMPT Receive Buffer Empty 12 1 read-only 0 Receive buffer contains valid data. #0 1 Receive buffer is empty, data returned on read is not valid. #1 FIFO LPUART FIFO Register 0x28 32 read-write n 0x0 0x0 RXEMPT Receive Buffer/FIFO Empty 22 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer depth = 1 dataword. #000 001 Receive FIFO/Buffer depth = 4 datawords. #001 010 Receive FIFO/Buffer depth = 8 datawords. #010 011 Receive FIFO/Buffer depth = 16 datawords. #011 100 Receive FIFO/Buffer depth = 32 datawords. #100 101 Receive FIFO/Buffer depth = 64 datawords. #101 110 Receive FIFO/Buffer depth = 128 datawords. #110 111 Receive FIFO/Buffer depth = 256 datawords. #111 RXFLUSH Receive FIFO/Buffer Flush 14 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 RXIDEN Receiver Idle Empty Enable 10 3 read-write 000 Disable RDRF assertion due to partially filled FIFO when receiver is idle. #000 001 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. #001 010 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. #010 011 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. #011 100 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. #100 101 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. #101 110 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. #110 111 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. #111 RXUF Receiver Buffer Underflow Flag 16 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 RXUFE Receive FIFO Underflow Interrupt Enable 8 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXEMPT Transmit Buffer/FIFO Empty 23 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer depth = 1 dataword. #000 001 Transmit FIFO/Buffer depth = 4 datawords. #001 010 Transmit FIFO/Buffer depth = 8 datawords. #010 011 Transmit FIFO/Buffer depth = 16 datawords. #011 100 Transmit FIFO/Buffer depth = 32 datawords. #100 101 Transmit FIFO/Buffer depth = 64 datawords. #101 110 Transmit FIFO/Buffer depth = 128 datawords. #110 111 Transmit FIFO/Buffer depth = 256 datawords #111 TXFLUSH Transmit FIFO/Buffer Flush 15 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 TXOF Transmitter Buffer Overflow Flag 17 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 9 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 GLOBAL LPUART Global Register 0x8 32 read-write n 0x0 0x0 RST Software Reset 1 1 read-write 0 Module is not reset. #0 1 Module is reset. #1 MATCH LPUART Match Address Register 0x20 32 read-write n 0x0 0x0 MA1 Match Address 1 0 10 read-write MA2 Match Address 2 16 10 read-write MODIR LPUART Modem IrDA Register 0x24 32 read-write n 0x0 0x0 IREN Infrared enable 18 1 read-write 0 IR disabled. #0 1 IR enabled. #1 RTSWATER Receive RTS Configuration 8 8 read-write 0 RTS asserts when the receiver FIFO is full or receiving a character that causes the FIFO to become full. #0 1 RTS asserts when the receive FIFO is less than or equal to the RXWATER configuration and negates when the receive FIFO is greater than the RXWATER configuration. #1 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS assertion is configured by the RTSWATER field #1 TNP Transmitter narrow pulse 16 2 read-write 00 1/OSR. #00 01 2/OSR. #01 10 3/OSR. #10 11 4/OSR. #11 TXCTSC Transmit CTS Configuration 4 1 read-write 0 CTS input is sampled at the start of each character. #0 1 CTS input is sampled when the transmitter is idle. #1 TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXCTSSRC Transmit CTS Source 5 1 read-write 0 CTS input is the LPUART_CTS pin. #0 1 CTS input is the inverted Receiver Match result. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 RXFIFO Receive FIFO Size 8 8 read-only TXFIFO Transmit FIFO Size 0 8 read-only PINCFG LPUART Pin Configuration Register 0xC 32 read-write n 0x0 0x0 TRGSEL Trigger Select 0 2 read-write 00 Input trigger is disabled. #00 01 Input trigger is used instead of RXD pin input. #01 10 Input trigger is used instead of CTS pin input. #10 11 Input trigger is used to modulate the TXD pin output. #11 STAT LPUART Status Register 0x14 32 read-write n 0x0 0x0 BRK13 Break Character Generation Length 26 1 read-write 0 Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). #0 1 Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1). #1 FE Framing Error Flag 17 1 read-write 0 No framing error detected. This does not guarantee the framing is correct. #0 1 Framing error. #1 IDLE Idle Line Flag 20 1 read-write 0 No idle line detected. #0 1 Idle line was detected. #1 LBKDE LIN Break Detection Enable 25 1 read-write 0 Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). #0 1 Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1). #1 LBKDIF LIN Break Detect Interrupt Flag 31 1 read-write 0 No LIN break character has been detected. #0 1 LIN break character has been detected. #1 MA1F Match 1 Flag 15 1 read-write 0 Received data is not equal to MA1 #0 1 Received data is equal to MA1 #1 MA2F Match 2 Flag 14 1 read-write 0 Received data is not equal to MA2 #0 1 Received data is equal to MA2 #1 MSBF MSB First 29 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. #1 NF Noise Flag 18 1 read-write 0 No noise detected. #0 1 Noise detected in the received character in LPUART_DATA. #1 OR Receiver Overrun Flag 19 1 read-write 0 No overrun. #0 1 Receive overrun (new LPUART data lost). #1 PF Parity Error Flag 16 1 read-write 0 No parity error. #0 1 Parity error. #1 RAF Receiver Active Flag 24 1 read-only 0 LPUART receiver idle waiting for a start bit. #0 1 LPUART receiver active (LPUART_RX input not idle). #1 RDRF Receive Data Register Full Flag 21 1 read-only 0 Receive data buffer empty. #0 1 Receive data buffer full. #1 RWUID Receive Wake Up Idle Detect 27 1 read-write 0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match. #0 1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match. #1 RXEDGIF LPUART_RX Pin Active Edge Interrupt Flag 30 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 RXINV Receive Data Inversion 28 1 read-write 0 Receive data not inverted. #0 1 Receive data inverted. #1 TC Transmission Complete Flag 22 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 23 1 read-only 0 Transmit data buffer full. #0 1 Transmit data buffer empty. #1 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Identification Number 0 16 read-only 1 Standard feature set. #1 11 Standard feature set with MODEM/IrDA support. #11 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only WATER LPUART Watermark Register 0x2C 32 read-write n 0x0 0x0 RXCOUNT Receive Counter 24 8 read-only RXWATER Receive Watermark 16 8 read-write TXCOUNT Transmit Counter 8 8 read-only TXWATER Transmit Watermark 0 8 read-write LPUART1 Universal Asynchronous Receiver/Transmitter LPUART 0x0 0x0 0x30 registers n LPUART1 13 BAUD LPUART Baud Rate Register 0x10 32 read-write n 0x0 0x0 BOTHEDGE Both Edge Sampling 17 1 read-write 0 Receiver samples input data using the rising edge of the baud rate clock. #0 1 Receiver samples input data using the rising and falling edge of the baud rate clock. #1 LBKDIE LIN Break Detect Interrupt Enable 15 1 read-write 0 Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). #0 1 Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. #1 M10 10-bit Mode select 29 1 read-write 0 Receiver and transmitter use 8-bit or 9-bit data characters. #0 1 Receiver and transmitter use 10-bit data characters. #1 MAEN1 Match Address Mode Enable 1 31 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA1]. #1 MAEN2 Match Address Mode Enable 2 30 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA2]. #1 MATCFG Match Configuration 18 2 read-write 00 Address Match Wakeup #00 01 Idle Match Wakeup #01 10 Match On and Match Off #10 11 Enables RWU on Data Match and Match On/Off for transmitter CTS input #11 OSR Oversampling Ratio 24 5 read-write RDMAE Receiver Full DMA Enable 21 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 RESYNCDIS Resynchronization Disable 16 1 read-write 0 Resynchronization during received data word is supported #0 1 Resynchronization during received data word is disabled #1 RXEDGIE RX Input Active Edge Interrupt Enable 14 1 read-write 0 Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling). #0 1 Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. #1 SBNS Stop Bit Number Select 13 1 read-write 0 One stop bit. #0 1 Two stop bits. #1 SBR Baud Rate Modulo Divisor. 0 13 read-write TDMAE Transmitter DMA Enable 23 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 CTRL LPUART Control Register 0x18 32 read-write n 0x0 0x0 DOZEEN Doze Enable 6 1 read-write 0 LPUART is enabled in Doze mode. #0 1 LPUART is disabled in Doze mode. #1 FEIE Framing Error Interrupt Enable 25 1 read-write 0 FE interrupts disabled; use polling. #0 1 Hardware interrupt requested when FE is set. #1 IDLECFG Idle Configuration 8 3 read-write 000 1 idle character #000 001 2 idle characters #001 010 4 idle characters #010 011 8 idle characters #011 100 16 idle characters #100 101 32 idle characters #101 110 64 idle characters #110 111 128 idle characters #111 ILIE Idle Line Interrupt Enable 20 1 read-write 0 Hardware interrupts from IDLE disabled; use polling. #0 1 Hardware interrupt requested when IDLE flag is 1. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation - LPUART_RX and LPUART_TX use separate pins. #0 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). #1 M 9-Bit or 8-Bit Mode Select 4 1 read-write 0 Receiver and transmitter use 8-bit data characters. #0 1 Receiver and transmitter use 9-bit data characters. #1 MA1IE Match 1 Interrupt Enable 15 1 read-write 0 MA1F interrupt disabled #0 1 MA1F interrupt enabled #1 MA2IE Match 2 Interrupt Enable 14 1 read-write 0 MA2F interrupt disabled #0 1 MA2F interrupt enabled #1 NEIE Noise Error Interrupt Enable 26 1 read-write 0 NF interrupts disabled; use polling. #0 1 Hardware interrupt requested when NF is set. #1 ORIE Overrun Interrupt Enable 27 1 read-write 0 OR interrupts disabled; use polling. #0 1 Hardware interrupt requested when OR is set. #1 PE Parity Enable 1 1 read-write 0 No hardware parity generation or checking. #0 1 Parity enabled. #1 PEIE Parity Error Interrupt Enable 24 1 read-write 0 PF interrupts disabled; use polling). #0 1 Hardware interrupt requested when PF is set. #1 PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 R8T9 Receive Bit 8 / Transmit Bit 9 31 1 read-write R9T8 Receive Bit 9 / Transmit Bit 8 30 1 read-write RE Receiver Enable 18 1 read-write 0 Receiver disabled. #0 1 Receiver enabled. #1 RIE Receiver Interrupt Enable 21 1 read-write 0 Hardware interrupts from RDRF disabled; use polling. #0 1 Hardware interrupt requested when RDRF flag is 1. #1 RSRC Receiver Source Select 5 1 read-write 0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin. #0 1 Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input. #1 RWU Receiver Wakeup Control 17 1 read-write 0 Normal receiver operation. #0 1 LPUART receiver in standby waiting for wakeup condition. #1 SBK Send Break 16 1 read-write 0 Normal transmitter operation. #0 1 Queue break character(s) to be sent. #1 TCIE Transmission Complete Interrupt Enable for 22 1 read-write 0 Hardware interrupts from TC disabled; use polling. #0 1 Hardware interrupt requested when TC flag is 1. #1 TE Transmitter Enable 19 1 read-write 0 Transmitter disabled. #0 1 Transmitter enabled. #1 TIE Transmit Interrupt Enable 23 1 read-write 0 Hardware interrupts from TDRE disabled; use polling. #0 1 Hardware interrupt requested when TDRE flag is 1. #1 TXDIR LPUART_TX Pin Direction in Single-Wire Mode 29 1 read-write 0 LPUART_TX pin is an input in single-wire mode. #0 1 LPUART_TX pin is an output in single-wire mode. #1 TXINV Transmit Data Inversion 28 1 read-write 0 Transmit data not inverted. #0 1 Transmit data inverted. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Configures RWU for idle-line wakeup. #0 1 Configures RWU with address-mark wakeup. #1 DATA LPUART Data Register 0x1C 32 read-write n 0x0 0x0 FRETSC Frame Error / Transmit Special Character 13 1 read-write 0 The dataword was received without a frame error on read, transmit a normal character on write. #0 1 The dataword was received with a frame error, transmit an idle or break character on transmit. #1 IDLINE Idle Line 11 1 read-only 0 Receiver was not idle before receiving this character. #0 1 Receiver was idle before receiving this character. #1 NOISY The current received dataword contained in DATA[R9:R0] was received with noise. 15 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 PARITYE The current received dataword contained in DATA[R9:R0] was received with a parity error. 14 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 R0T0 Read receive data buffer 0 or write transmit data buffer 0. 0 1 read-write R1T1 Read receive data buffer 1 or write transmit data buffer 1. 1 1 read-write R2T2 Read receive data buffer 2 or write transmit data buffer 2. 2 1 read-write R3T3 Read receive data buffer 3 or write transmit data buffer 3. 3 1 read-write R4T4 Read receive data buffer 4 or write transmit data buffer 4. 4 1 read-write R5T5 Read receive data buffer 5 or write transmit data buffer 5. 5 1 read-write R6T6 Read receive data buffer 6 or write transmit data buffer 6. 6 1 read-write R7T7 Read receive data buffer 7 or write transmit data buffer 7. 7 1 read-write R8T8 Read receive data buffer 8 or write transmit data buffer 8. 8 1 read-write R9T9 Read receive data buffer 9 or write transmit data buffer 9. 9 1 read-write RXEMPT Receive Buffer Empty 12 1 read-only 0 Receive buffer contains valid data. #0 1 Receive buffer is empty, data returned on read is not valid. #1 FIFO LPUART FIFO Register 0x28 32 read-write n 0x0 0x0 RXEMPT Receive Buffer/FIFO Empty 22 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer depth = 1 dataword. #000 001 Receive FIFO/Buffer depth = 4 datawords. #001 010 Receive FIFO/Buffer depth = 8 datawords. #010 011 Receive FIFO/Buffer depth = 16 datawords. #011 100 Receive FIFO/Buffer depth = 32 datawords. #100 101 Receive FIFO/Buffer depth = 64 datawords. #101 110 Receive FIFO/Buffer depth = 128 datawords. #110 111 Receive FIFO/Buffer depth = 256 datawords. #111 RXFLUSH Receive FIFO/Buffer Flush 14 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 RXIDEN Receiver Idle Empty Enable 10 3 read-write 000 Disable RDRF assertion due to partially filled FIFO when receiver is idle. #000 001 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. #001 010 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. #010 011 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. #011 100 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. #100 101 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. #101 110 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. #110 111 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. #111 RXUF Receiver Buffer Underflow Flag 16 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 RXUFE Receive FIFO Underflow Interrupt Enable 8 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXEMPT Transmit Buffer/FIFO Empty 23 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer depth = 1 dataword. #000 001 Transmit FIFO/Buffer depth = 4 datawords. #001 010 Transmit FIFO/Buffer depth = 8 datawords. #010 011 Transmit FIFO/Buffer depth = 16 datawords. #011 100 Transmit FIFO/Buffer depth = 32 datawords. #100 101 Transmit FIFO/Buffer depth = 64 datawords. #101 110 Transmit FIFO/Buffer depth = 128 datawords. #110 111 Transmit FIFO/Buffer depth = 256 datawords #111 TXFLUSH Transmit FIFO/Buffer Flush 15 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 TXOF Transmitter Buffer Overflow Flag 17 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 9 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 GLOBAL LPUART Global Register 0x8 32 read-write n 0x0 0x0 RST Software Reset 1 1 read-write 0 Module is not reset. #0 1 Module is reset. #1 MATCH LPUART Match Address Register 0x20 32 read-write n 0x0 0x0 MA1 Match Address 1 0 10 read-write MA2 Match Address 2 16 10 read-write MODIR LPUART Modem IrDA Register 0x24 32 read-write n 0x0 0x0 IREN Infrared enable 18 1 read-write 0 IR disabled. #0 1 IR enabled. #1 RTSWATER Receive RTS Configuration 8 8 read-write 0 RTS asserts when the receiver FIFO is full or receiving a character that causes the FIFO to become full. #0 1 RTS asserts when the receive FIFO is less than or equal to the RXWATER configuration and negates when the receive FIFO is greater than the RXWATER configuration. #1 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS assertion is configured by the RTSWATER field #1 TNP Transmitter narrow pulse 16 2 read-write 00 1/OSR. #00 01 2/OSR. #01 10 3/OSR. #10 11 4/OSR. #11 TXCTSC Transmit CTS Configuration 4 1 read-write 0 CTS input is sampled at the start of each character. #0 1 CTS input is sampled when the transmitter is idle. #1 TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXCTSSRC Transmit CTS Source 5 1 read-write 0 CTS input is the LPUART_CTS pin. #0 1 CTS input is the inverted Receiver Match result. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 RXFIFO Receive FIFO Size 8 8 read-only TXFIFO Transmit FIFO Size 0 8 read-only PINCFG LPUART Pin Configuration Register 0xC 32 read-write n 0x0 0x0 TRGSEL Trigger Select 0 2 read-write 00 Input trigger is disabled. #00 01 Input trigger is used instead of RXD pin input. #01 10 Input trigger is used instead of CTS pin input. #10 11 Input trigger is used to modulate the TXD pin output. #11 STAT LPUART Status Register 0x14 32 read-write n 0x0 0x0 BRK13 Break Character Generation Length 26 1 read-write 0 Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). #0 1 Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1). #1 FE Framing Error Flag 17 1 read-write 0 No framing error detected. This does not guarantee the framing is correct. #0 1 Framing error. #1 IDLE Idle Line Flag 20 1 read-write 0 No idle line detected. #0 1 Idle line was detected. #1 LBKDE LIN Break Detection Enable 25 1 read-write 0 Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). #0 1 Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1). #1 LBKDIF LIN Break Detect Interrupt Flag 31 1 read-write 0 No LIN break character has been detected. #0 1 LIN break character has been detected. #1 MA1F Match 1 Flag 15 1 read-write 0 Received data is not equal to MA1 #0 1 Received data is equal to MA1 #1 MA2F Match 2 Flag 14 1 read-write 0 Received data is not equal to MA2 #0 1 Received data is equal to MA2 #1 MSBF MSB First 29 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. #1 NF Noise Flag 18 1 read-write 0 No noise detected. #0 1 Noise detected in the received character in LPUART_DATA. #1 OR Receiver Overrun Flag 19 1 read-write 0 No overrun. #0 1 Receive overrun (new LPUART data lost). #1 PF Parity Error Flag 16 1 read-write 0 No parity error. #0 1 Parity error. #1 RAF Receiver Active Flag 24 1 read-only 0 LPUART receiver idle waiting for a start bit. #0 1 LPUART receiver active (LPUART_RX input not idle). #1 RDRF Receive Data Register Full Flag 21 1 read-only 0 Receive data buffer empty. #0 1 Receive data buffer full. #1 RWUID Receive Wake Up Idle Detect 27 1 read-write 0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match. #0 1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match. #1 RXEDGIF LPUART_RX Pin Active Edge Interrupt Flag 30 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 RXINV Receive Data Inversion 28 1 read-write 0 Receive data not inverted. #0 1 Receive data inverted. #1 TC Transmission Complete Flag 22 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 23 1 read-only 0 Transmit data buffer full. #0 1 Transmit data buffer empty. #1 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Identification Number 0 16 read-only 1 Standard feature set. #1 11 Standard feature set with MODEM/IrDA support. #11 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only WATER LPUART Watermark Register 0x2C 32 read-write n 0x0 0x0 RXCOUNT Receive Counter 24 8 read-only RXWATER Receive Watermark 16 8 read-write TXCOUNT Transmit Counter 8 8 read-only TXWATER Transmit Watermark 0 8 read-write LPUART2 Universal Asynchronous Receiver/Transmitter LPUART 0x0 0x0 0x30 registers n LPUART2 37 BAUD LPUART Baud Rate Register 0x10 32 read-write n 0x0 0x0 BOTHEDGE Both Edge Sampling 17 1 read-write 0 Receiver samples input data using the rising edge of the baud rate clock. #0 1 Receiver samples input data using the rising and falling edge of the baud rate clock. #1 LBKDIE LIN Break Detect Interrupt Enable 15 1 read-write 0 Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). #0 1 Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. #1 M10 10-bit Mode select 29 1 read-write 0 Receiver and transmitter use 8-bit or 9-bit data characters. #0 1 Receiver and transmitter use 10-bit data characters. #1 MAEN1 Match Address Mode Enable 1 31 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA1]. #1 MAEN2 Match Address Mode Enable 2 30 1 read-write 0 Normal operation. #0 1 Enables automatic address matching or data matching mode for MATCH[MA2]. #1 MATCFG Match Configuration 18 2 read-write 00 Address Match Wakeup #00 01 Idle Match Wakeup #01 10 Match On and Match Off #10 11 Enables RWU on Data Match and Match On/Off for transmitter CTS input #11 OSR Oversampling Ratio 24 5 read-write RDMAE Receiver Full DMA Enable 21 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 RESYNCDIS Resynchronization Disable 16 1 read-write 0 Resynchronization during received data word is supported #0 1 Resynchronization during received data word is disabled #1 RXEDGIE RX Input Active Edge Interrupt Enable 14 1 read-write 0 Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling). #0 1 Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. #1 SBNS Stop Bit Number Select 13 1 read-write 0 One stop bit. #0 1 Two stop bits. #1 SBR Baud Rate Modulo Divisor. 0 13 read-write TDMAE Transmitter DMA Enable 23 1 read-write 0 DMA request disabled. #0 1 DMA request enabled. #1 CTRL LPUART Control Register 0x18 32 read-write n 0x0 0x0 DOZEEN Doze Enable 6 1 read-write 0 LPUART is enabled in Doze mode. #0 1 LPUART is disabled in Doze mode. #1 FEIE Framing Error Interrupt Enable 25 1 read-write 0 FE interrupts disabled; use polling. #0 1 Hardware interrupt requested when FE is set. #1 IDLECFG Idle Configuration 8 3 read-write 000 1 idle character #000 001 2 idle characters #001 010 4 idle characters #010 011 8 idle characters #011 100 16 idle characters #100 101 32 idle characters #101 110 64 idle characters #110 111 128 idle characters #111 ILIE Idle Line Interrupt Enable 20 1 read-write 0 Hardware interrupts from IDLE disabled; use polling. #0 1 Hardware interrupt requested when IDLE flag is 1. #1 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation - LPUART_RX and LPUART_TX use separate pins. #0 1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). #1 M 9-Bit or 8-Bit Mode Select 4 1 read-write 0 Receiver and transmitter use 8-bit data characters. #0 1 Receiver and transmitter use 9-bit data characters. #1 MA1IE Match 1 Interrupt Enable 15 1 read-write 0 MA1F interrupt disabled #0 1 MA1F interrupt enabled #1 MA2IE Match 2 Interrupt Enable 14 1 read-write 0 MA2F interrupt disabled #0 1 MA2F interrupt enabled #1 NEIE Noise Error Interrupt Enable 26 1 read-write 0 NF interrupts disabled; use polling. #0 1 Hardware interrupt requested when NF is set. #1 ORIE Overrun Interrupt Enable 27 1 read-write 0 OR interrupts disabled; use polling. #0 1 Hardware interrupt requested when OR is set. #1 PE Parity Enable 1 1 read-write 0 No hardware parity generation or checking. #0 1 Parity enabled. #1 PEIE Parity Error Interrupt Enable 24 1 read-write 0 PF interrupts disabled; use polling). #0 1 Hardware interrupt requested when PF is set. #1 PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 R8T9 Receive Bit 8 / Transmit Bit 9 31 1 read-write R9T8 Receive Bit 9 / Transmit Bit 8 30 1 read-write RE Receiver Enable 18 1 read-write 0 Receiver disabled. #0 1 Receiver enabled. #1 RIE Receiver Interrupt Enable 21 1 read-write 0 Hardware interrupts from RDRF disabled; use polling. #0 1 Hardware interrupt requested when RDRF flag is 1. #1 RSRC Receiver Source Select 5 1 read-write 0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin. #0 1 Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input. #1 RWU Receiver Wakeup Control 17 1 read-write 0 Normal receiver operation. #0 1 LPUART receiver in standby waiting for wakeup condition. #1 SBK Send Break 16 1 read-write 0 Normal transmitter operation. #0 1 Queue break character(s) to be sent. #1 TCIE Transmission Complete Interrupt Enable for 22 1 read-write 0 Hardware interrupts from TC disabled; use polling. #0 1 Hardware interrupt requested when TC flag is 1. #1 TE Transmitter Enable 19 1 read-write 0 Transmitter disabled. #0 1 Transmitter enabled. #1 TIE Transmit Interrupt Enable 23 1 read-write 0 Hardware interrupts from TDRE disabled; use polling. #0 1 Hardware interrupt requested when TDRE flag is 1. #1 TXDIR LPUART_TX Pin Direction in Single-Wire Mode 29 1 read-write 0 LPUART_TX pin is an input in single-wire mode. #0 1 LPUART_TX pin is an output in single-wire mode. #1 TXINV Transmit Data Inversion 28 1 read-write 0 Transmit data not inverted. #0 1 Transmit data inverted. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Configures RWU for idle-line wakeup. #0 1 Configures RWU with address-mark wakeup. #1 DATA LPUART Data Register 0x1C 32 read-write n 0x0 0x0 FRETSC Frame Error / Transmit Special Character 13 1 read-write 0 The dataword was received without a frame error on read, transmit a normal character on write. #0 1 The dataword was received with a frame error, transmit an idle or break character on transmit. #1 IDLINE Idle Line 11 1 read-only 0 Receiver was not idle before receiving this character. #0 1 Receiver was idle before receiving this character. #1 NOISY The current received dataword contained in DATA[R9:R0] was received with noise. 15 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 PARITYE The current received dataword contained in DATA[R9:R0] was received with a parity error. 14 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 R0T0 Read receive data buffer 0 or write transmit data buffer 0. 0 1 read-write R1T1 Read receive data buffer 1 or write transmit data buffer 1. 1 1 read-write R2T2 Read receive data buffer 2 or write transmit data buffer 2. 2 1 read-write R3T3 Read receive data buffer 3 or write transmit data buffer 3. 3 1 read-write R4T4 Read receive data buffer 4 or write transmit data buffer 4. 4 1 read-write R5T5 Read receive data buffer 5 or write transmit data buffer 5. 5 1 read-write R6T6 Read receive data buffer 6 or write transmit data buffer 6. 6 1 read-write R7T7 Read receive data buffer 7 or write transmit data buffer 7. 7 1 read-write R8T8 Read receive data buffer 8 or write transmit data buffer 8. 8 1 read-write R9T9 Read receive data buffer 9 or write transmit data buffer 9. 9 1 read-write RXEMPT Receive Buffer Empty 12 1 read-only 0 Receive buffer contains valid data. #0 1 Receive buffer is empty, data returned on read is not valid. #1 FIFO LPUART FIFO Register 0x28 32 read-write n 0x0 0x0 RXEMPT Receive Buffer/FIFO Empty 22 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer depth = 1 dataword. #000 001 Receive FIFO/Buffer depth = 4 datawords. #001 010 Receive FIFO/Buffer depth = 8 datawords. #010 011 Receive FIFO/Buffer depth = 16 datawords. #011 100 Receive FIFO/Buffer depth = 32 datawords. #100 101 Receive FIFO/Buffer depth = 64 datawords. #101 110 Receive FIFO/Buffer depth = 128 datawords. #110 111 Receive FIFO/Buffer depth = 256 datawords. #111 RXFLUSH Receive FIFO/Buffer Flush 14 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 RXIDEN Receiver Idle Empty Enable 10 3 read-write 000 Disable RDRF assertion due to partially filled FIFO when receiver is idle. #000 001 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. #001 010 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. #010 011 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. #011 100 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. #100 101 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. #101 110 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. #110 111 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. #111 RXUF Receiver Buffer Underflow Flag 16 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 RXUFE Receive FIFO Underflow Interrupt Enable 8 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXEMPT Transmit Buffer/FIFO Empty 23 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer depth = 1 dataword. #000 001 Transmit FIFO/Buffer depth = 4 datawords. #001 010 Transmit FIFO/Buffer depth = 8 datawords. #010 011 Transmit FIFO/Buffer depth = 16 datawords. #011 100 Transmit FIFO/Buffer depth = 32 datawords. #100 101 Transmit FIFO/Buffer depth = 64 datawords. #101 110 Transmit FIFO/Buffer depth = 128 datawords. #110 111 Transmit FIFO/Buffer depth = 256 datawords #111 TXFLUSH Transmit FIFO/Buffer Flush 15 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 TXOF Transmitter Buffer Overflow Flag 17 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 9 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 GLOBAL LPUART Global Register 0x8 32 read-write n 0x0 0x0 RST Software Reset 1 1 read-write 0 Module is not reset. #0 1 Module is reset. #1 MATCH LPUART Match Address Register 0x20 32 read-write n 0x0 0x0 MA1 Match Address 1 0 10 read-write MA2 Match Address 2 16 10 read-write MODIR LPUART Modem IrDA Register 0x24 32 read-write n 0x0 0x0 IREN Infrared enable 18 1 read-write 0 IR disabled. #0 1 IR enabled. #1 RTSWATER Receive RTS Configuration 8 8 read-write 0 RTS asserts when the receiver FIFO is full or receiving a character that causes the FIFO to become full. #0 1 RTS asserts when the receive FIFO is less than or equal to the RXWATER configuration and negates when the receive FIFO is greater than the RXWATER configuration. #1 RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS assertion is configured by the RTSWATER field #1 TNP Transmitter narrow pulse 16 2 read-write 00 1/OSR. #00 01 2/OSR. #01 10 3/OSR. #10 11 4/OSR. #11 TXCTSC Transmit CTS Configuration 4 1 read-write 0 CTS input is sampled at the start of each character. #0 1 CTS input is sampled when the transmitter is idle. #1 TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXCTSSRC Transmit CTS Source 5 1 read-write 0 CTS input is the LPUART_CTS pin. #0 1 CTS input is the inverted Receiver Match result. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 RXFIFO Receive FIFO Size 8 8 read-only TXFIFO Transmit FIFO Size 0 8 read-only PINCFG LPUART Pin Configuration Register 0xC 32 read-write n 0x0 0x0 TRGSEL Trigger Select 0 2 read-write 00 Input trigger is disabled. #00 01 Input trigger is used instead of RXD pin input. #01 10 Input trigger is used instead of CTS pin input. #10 11 Input trigger is used to modulate the TXD pin output. #11 STAT LPUART Status Register 0x14 32 read-write n 0x0 0x0 BRK13 Break Character Generation Length 26 1 read-write 0 Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). #0 1 Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1). #1 FE Framing Error Flag 17 1 read-write 0 No framing error detected. This does not guarantee the framing is correct. #0 1 Framing error. #1 IDLE Idle Line Flag 20 1 read-write 0 No idle line detected. #0 1 Idle line was detected. #1 LBKDE LIN Break Detection Enable 25 1 read-write 0 Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1). #0 1 Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1). #1 LBKDIF LIN Break Detect Interrupt Flag 31 1 read-write 0 No LIN break character has been detected. #0 1 LIN break character has been detected. #1 MA1F Match 1 Flag 15 1 read-write 0 Received data is not equal to MA1 #0 1 Received data is equal to MA1 #1 MA2F Match 2 Flag 14 1 read-write 0 Received data is not equal to MA2 #0 1 Received data is equal to MA2 #1 MSBF MSB First 29 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. #1 NF Noise Flag 18 1 read-write 0 No noise detected. #0 1 Noise detected in the received character in LPUART_DATA. #1 OR Receiver Overrun Flag 19 1 read-write 0 No overrun. #0 1 Receive overrun (new LPUART data lost). #1 PF Parity Error Flag 16 1 read-write 0 No parity error. #0 1 Parity error. #1 RAF Receiver Active Flag 24 1 read-only 0 LPUART receiver idle waiting for a start bit. #0 1 LPUART receiver active (LPUART_RX input not idle). #1 RDRF Receive Data Register Full Flag 21 1 read-only 0 Receive data buffer empty. #0 1 Receive data buffer full. #1 RWUID Receive Wake Up Idle Detect 27 1 read-write 0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match. #0 1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match. #1 RXEDGIF LPUART_RX Pin Active Edge Interrupt Flag 30 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 RXINV Receive Data Inversion 28 1 read-write 0 Receive data not inverted. #0 1 Receive data inverted. #1 TC Transmission Complete Flag 22 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 23 1 read-only 0 Transmit data buffer full. #0 1 Transmit data buffer empty. #1 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Identification Number 0 16 read-only 1 Standard feature set. #1 11 Standard feature set with MODEM/IrDA support. #11 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only WATER LPUART Watermark Register 0x2C 32 read-write n 0x0 0x0 RXCOUNT Receive Counter 24 8 read-only RXWATER Receive Watermark 16 8 read-write TXCOUNT Transmit Counter 8 8 read-only TXWATER Transmit Watermark 0 8 read-write MCM0 Core Platform Miscellaneous Control Module MCM 0x0 0x8 0x3C registers n CPO Compute Operation Control Register 0x40 32 read-write n 0x0 0x0 CPOACK Compute Operation Acknowledge 1 1 read-only 0 Compute operation entry has not completed or compute operation exit has completed. #0 1 Compute operation entry has completed or compute operation exit has not completed. #1 CPOREQ Compute Operation Request 0 1 read-write 0 Request is cleared. #0 1 Request Compute Operation. #1 CPOWOI Compute Operation Wake-up on Interrupt 2 1 read-write 0 No effect. #0 1 When set, the CPOREQ is cleared on any interrupt or exception vector fetch. #1 PLACR Platform Control Register 0xC 32 read-write n 0x0 0x0 ARB Arbitration select 9 1 read-write 0 Fixed-priority arbitration for the crossbar masters #0 1 Round-robin arbitration for the crossbar masters #1 CFCC Clear Flash Controller Cache 10 1 write-only DFCC Disable Flash Controller Cache 13 1 read-write 0 Enable flash controller cache. #0 1 Disable flash controller cache. #1 DFCDA Disable Flash Controller Data Caching 11 1 read-write 0 Enable flash controller data caching #0 1 Disable flash controller data caching. #1 DFCIC Disable Flash Controller Instruction Caching 12 1 read-write 0 Enable flash controller instruction caching. #0 1 Disable flash controller instruction caching. #1 DFCS Disable Flash Controller Speculation 15 1 read-write 0 Enable flash controller speculation. #0 1 Disable flash controller speculation. #1 EFDS Enable Flash Data Speculation 14 1 read-write 0 Disable flash data speculation. #0 1 Enable flash data speculation. #1 ESFC Enable Stalling Flash Controller 16 1 read-write 0 Disable stalling flash controller when flash is busy. #0 1 Enable stalling flash controller when flash is busy. #1 MMCAU MMCAU Present 8 1 read-only 0 MMCAU is disabled #0 1 MMCAU is enabled #1 PLAMC Crossbar Switch (AXBS) Master Configuration 0xA 16 read-only n 0x0 0x0 AMC Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 0 8 read-only 0 A bus master connection to AXBS input port n is absent #0 1 A bus master connection to AXBS input port n is present #1 PLASC Crossbar Switch (AXBS) Slave Configuration 0x8 16 read-only n 0x0 0x0 ASC Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 0 8 read-only 0 A bus slave connection to AXBS input port n is absent. #0 1 A bus slave connection to AXBS input port n is present. #1 MCM1 Core Platform Miscellaneous Control Module MCM 0x0 0x8 0x3C registers n CPO Compute Operation Control Register 0x40 32 read-write n 0x0 0x0 CPOACK Compute Operation Acknowledge 1 1 read-only 0 Compute operation entry has not completed or compute operation exit has completed. #0 1 Compute operation entry has completed or compute operation exit has not completed. #1 CPOREQ Compute Operation Request 0 1 read-write 0 Request is cleared. #0 1 Request Compute Operation. #1 CPOWOI Compute Operation Wake-up on Interrupt 2 1 read-write 0 No effect. #0 1 When set, the CPOREQ is cleared on any interrupt or exception vector fetch. #1 PLACR Platform Control Register 0xC 32 read-write n 0x0 0x0 ARB Arbitration select 9 1 read-write 0 Fixed-priority arbitration for the crossbar masters #0 1 Round-robin arbitration for the crossbar masters #1 CFCC Clear Flash Controller Cache 10 1 write-only DFCC Disable Flash Controller Cache 13 1 read-write 0 Enable flash controller cache. #0 1 Disable flash controller cache. #1 DFCDA Disable Flash Controller Data Caching 11 1 read-write 0 Enable flash controller data caching #0 1 Disable flash controller data caching. #1 DFCIC Disable Flash Controller Instruction Caching 12 1 read-write 0 Enable flash controller instruction caching. #0 1 Disable flash controller instruction caching. #1 DFCS Disable Flash Controller Speculation 15 1 read-write 0 Enable flash controller speculation. #0 1 Disable flash controller speculation. #1 EFDS Enable Flash Data Speculation 14 1 read-write 0 Disable flash data speculation. #0 1 Enable flash data speculation. #1 ESFC Enable Stalling Flash Controller 16 1 read-write 0 Disable stalling flash controller when flash is busy. #0 1 Enable stalling flash controller when flash is busy. #1 MMCAU MMCAU Present 8 1 read-only 0 MMCAU is disabled #0 1 MMCAU is enabled #1 PLAMC Crossbar Switch (AXBS) Master Configuration 0xA 16 read-only n 0x0 0x0 AMC Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 0 8 read-only 0 A bus master connection to AXBS input port n is absent #0 1 A bus master connection to AXBS input port n is present #1 PLASC Crossbar Switch (AXBS) Slave Configuration 0x8 16 read-only n 0x0 0x0 ASC Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 0 8 read-only 0 A bus slave connection to AXBS input port n is absent. #0 1 A bus slave connection to AXBS input port n is present. #1 MMDVSQ0 Divide and Square Root MMDVSQ 0x0 0x0 0x14 registers n CSR Control/Status Register 0x8 32 read-write n 0x0 0x0 BUSY BUSY 31 1 read-only 0 MMDVSQ is idle #0 1 MMDVSQ is busy performing a divide or square root calculation #1 DFS Disable Fast Start 5 1 read-write 0 A divide operation is initiated by a write to the DSOR register #0 1 A divide operation is initiated by a write to the CSR register with CSR[SRT] = 1 #1 DIV DIVIDE 30 1 read-only 0 Current or last MMDVSQ operation was not a divide #0 1 Current or last MMDVSQ operation was a divide #1 DZ Divide-by-Zero 4 1 read-only 0 The last divide operation had a non-zero divisor, that is, DSOR != 0 #0 1 The last divide operation had a zero divisor, that is, DSOR = 0 #1 DZE Divide-by-Zero-Enable 3 1 read-write 0 Reads of the RES register return the register contents #0 1 If CSR[DZ] = 1, an attempted read of RES register is error terminated to signal a divide-by-zero, else the register contents are returned #1 REM REMainder calculation 2 1 read-write 0 Return the quotient in the RES for the divide calculation #0 1 Return the remainder in the RES for the divide calculation #1 SQRT SQUARE ROOT 29 1 read-only 0 Current or last MMDVSQ operation was not a square root #0 1 Current or last MMDVSQ operation was a square root #1 SRT Start 0 1 write-only 0 No operation initiated #0 1 If CSR[DFS] = 1, then initiate a divide calculation, else ignore #1 USGN Unsigned calculation 1 1 read-write 0 Perform a signed divide #0 1 Perform an unsigned divide #1 DEND Dividend Register 0x0 32 read-write n 0x0 0x0 DIVIDEND Dividend 0 32 read-write DSOR Divisor Register 0x4 32 read-write n 0x0 0x0 DIVISOR Divisor 0 32 read-write RCND Radicand Register 0x10 32 read-write n 0x0 0x0 RADICAND Radicand 0 32 read-write RES Result Register 0xC 32 read-write n 0x0 0x0 RESULT Result 0 32 read-write MMDVSQ1 Divide and Square Root MMDVSQ 0x0 0x0 0x14 registers n CSR Control/Status Register 0x8 32 read-write n 0x0 0x0 BUSY BUSY 31 1 read-only 0 MMDVSQ is idle #0 1 MMDVSQ is busy performing a divide or square root calculation #1 DFS Disable Fast Start 5 1 read-write 0 A divide operation is initiated by a write to the DSOR register #0 1 A divide operation is initiated by a write to the CSR register with CSR[SRT] = 1 #1 DIV DIVIDE 30 1 read-only 0 Current or last MMDVSQ operation was not a divide #0 1 Current or last MMDVSQ operation was a divide #1 DZ Divide-by-Zero 4 1 read-only 0 The last divide operation had a non-zero divisor, that is, DSOR != 0 #0 1 The last divide operation had a zero divisor, that is, DSOR = 0 #1 DZE Divide-by-Zero-Enable 3 1 read-write 0 Reads of the RES register return the register contents #0 1 If CSR[DZ] = 1, an attempted read of RES register is error terminated to signal a divide-by-zero, else the register contents are returned #1 REM REMainder calculation 2 1 read-write 0 Return the quotient in the RES for the divide calculation #0 1 Return the remainder in the RES for the divide calculation #1 SQRT SQUARE ROOT 29 1 read-only 0 Current or last MMDVSQ operation was not a square root #0 1 Current or last MMDVSQ operation was a square root #1 SRT Start 0 1 write-only 0 No operation initiated #0 1 If CSR[DFS] = 1, then initiate a divide calculation, else ignore #1 USGN Unsigned calculation 1 1 read-write 0 Perform a signed divide #0 1 Perform an unsigned divide #1 DEND Dividend Register 0x0 32 read-write n 0x0 0x0 DIVIDEND Dividend 0 32 read-write DSOR Divisor Register 0x4 32 read-write n 0x0 0x0 DIVISOR Divisor 0 32 read-write RCND Radicand Register 0x10 32 read-write n 0x0 0x0 RADICAND Radicand 0 32 read-write RES Result Register 0xC 32 read-write n 0x0 0x0 RESULT Result 0 32 read-write MSCM MSCM MSCM 0x0 0x0 0x40C registers n CP0CFG0 Processor 0 Configuration Register 0x60 32 read-only n 0x0 0x0 DCSZ Level 1 Data Cache Size 8 8 read-only DCWY Level 1 Data Cache Ways 0 8 read-only ICSZ Level 1 Instruction Cache Size 24 8 read-only ICWY Level 1 Instruction Cache Ways 16 8 read-only CP0CFG1 Processor 0 Configuration Register 0x94 32 read-only n 0x0 0x0 DCSZ Level 1 Data Cache Size 8 8 read-only DCWY Level 1 Data Cache Ways 0 8 read-only ICSZ Level 1 Instruction Cache Size 24 8 read-only ICWY Level 1 Instruction Cache Ways 16 8 read-only CP0CFG2 Processor 0 Configuration Register 0xCC 32 read-only n 0x0 0x0 DCSZ Level 1 Data Cache Size 8 8 read-only DCWY Level 1 Data Cache Ways 0 8 read-only ICSZ Level 1 Instruction Cache Size 24 8 read-only ICWY Level 1 Instruction Cache Ways 16 8 read-only CP0CFG3 Processor 0 Configuration Register 0x108 32 read-only n 0x0 0x0 DCSZ Level 1 Data Cache Size 8 8 read-only DCWY Level 1 Data Cache Ways 0 8 read-only ICSZ Level 1 Instruction Cache Size 24 8 read-only ICWY Level 1 Instruction Cache Ways 16 8 read-only CP0COUNT Processor 0 Count Register 0x2C 32 read-only n 0x0 0x0 PCNT Processor Count 0 2 read-only CP0MASTER Processor 0 Master Register 0x28 32 read-only n 0x0 0x0 PPN Processor x Physical Port Number 0 6 read-only CP0NUM Processor 0 Number Register 0x24 32 read-only n 0x0 0x0 CPN Processor x Number 0 1 read-only CP0TYPE Processor 0 Type Register 0x20 32 read-only n 0x0 0x0 PERSONALITY Processor x Personality 8 24 read-only RYPZ Processor x Revision 0 8 read-only CP1CFG0 Processor 1 Configuration Register 0xA0 32 read-only n 0x0 0x0 DCSZ Level 1 Data Cache Size 8 8 read-only DCWY Level 1 Data Cache Ways 0 8 read-only ICSZ Level 1 Instruction Cache Size 24 8 read-only ICWY Level 1 Instruction Cache Ways 16 8 read-only CP1CFG1 Processor 1 Configuration Register 0xF4 32 read-only n 0x0 0x0 DCSZ Level 1 Data Cache Size 8 8 read-only DCWY Level 1 Data Cache Ways 0 8 read-only ICSZ Level 1 Instruction Cache Size 24 8 read-only ICWY Level 1 Instruction Cache Ways 16 8 read-only CP1CFG2 Processor 1 Configuration Register 0x14C 32 read-only n 0x0 0x0 DCSZ Level 1 Data Cache Size 8 8 read-only DCWY Level 1 Data Cache Ways 0 8 read-only ICSZ Level 1 Instruction Cache Size 24 8 read-only ICWY Level 1 Instruction Cache Ways 16 8 read-only CP1CFG3 Processor 1 Configuration Register 0x1A8 32 read-only n 0x0 0x0 DCSZ Level 1 Data Cache Size 8 8 read-only DCWY Level 1 Data Cache Ways 0 8 read-only ICSZ Level 1 Instruction Cache Size 24 8 read-only ICWY Level 1 Instruction Cache Ways 16 8 read-only CP1COUNT Processor 1 Count Register 0x4C 32 read-only n 0x0 0x0 PCNT Processor Count 0 2 read-only CP1MASTER Processor 1 Master Register 0x48 32 read-only n 0x0 0x0 PPN Processor x Physical Port Number 0 6 read-only CP1NUM Processor 1 Number Register 0x44 32 read-only n 0x0 0x0 CPN Processor x Number 0 1 read-only CP1TYPE Processor 1 Type Register 0x40 32 read-only n 0x0 0x0 PERSONALITY Processor x Personality 8 24 read-only RYPZ Processor x Revision 0 8 read-only CPxCFG0 Processor X Configuration Register 0x20 32 read-only n 0x0 0x0 DCSZ Level 1 Data Cache Size 8 8 read-only DCWY Level 1 Data Cache Ways 0 8 read-only ICSZ Level 1 Instruction Cache Size 24 8 read-only ICWY Level 1 Instruction Cache Ways 16 8 read-only CPxCFG1 Processor X Configuration Register 0x34 32 read-only n 0x0 0x0 DCSZ Level 1 Data Cache Size 8 8 read-only DCWY Level 1 Data Cache Ways 0 8 read-only ICSZ Level 1 Instruction Cache Size 24 8 read-only ICWY Level 1 Instruction Cache Ways 16 8 read-only CPxCFG2 Processor X Configuration Register 0x4C 32 read-only n 0x0 0x0 DCSZ Level 1 Data Cache Size 8 8 read-only DCWY Level 1 Data Cache Ways 0 8 read-only ICSZ Level 1 Instruction Cache Size 24 8 read-only ICWY Level 1 Instruction Cache Ways 16 8 read-only CPxCFG3 Processor X Configuration Register 0x68 32 read-only n 0x0 0x0 DCSZ Level 1 Data Cache Size 8 8 read-only DCWY Level 1 Data Cache Ways 0 8 read-only ICSZ Level 1 Instruction Cache Size 24 8 read-only ICWY Level 1 Instruction Cache Ways 16 8 read-only CPxCOUNT Processor X Count Register 0xC 32 read-only n 0x0 0x0 PCNT Processor Count 0 2 read-only CPxMASTER Processor X Master Register 0x8 32 read-only n 0x0 0x0 PPN Processor x Physical Port Number 0 6 read-only CPxNUM Processor X Number Register 0x4 32 read-only n 0x0 0x0 CPN Processor x Number 0 1 read-only CPxTYPE Processor X Type Register 0x0 32 read-only n 0x0 0x0 PERSONALITY Processor x Personality 8 24 read-only RYPZ Processor x Revision 0 8 read-only OCMDR0 On-Chip Memory Descriptor Register 0x800 32 read-only n 0x0 0x0 OCMPU OCMEM Memory Protection Unit. This read-only field identifies a memory protected by an XRDC module. 12 1 read-only 0 OCMEMn is not protected by an XRDC module. #0 1 OCMEMn is protected by an XRDC module. #1 OCMSZ OCMEM Size 24 4 read-only 0000 no OCMEMn #0000 0100 4KB OCMEMn #0100 0101 8KB OCMEMn #0101 0110 16KB OCMEMn #0110 0111 32KB OCMEMn #0111 1111 8192KB OCMEMn #1111 OCMSZH OCMEM Size "Hole" 28 1 read-only 0 OCMEMn is a power-of-2 capacity. #0 1 OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. #1 OCMT OCMEM Type. This field defines the type of the on-chip memory: 13 3 read-only 000 OCMEMn is a system RAM. #000 001 OCMEMn is a graphics RAM. #001 011 OCMEMn is a ROM. #011 OCMW OCMEM datapath Width. This read-only field defines the width of the on-chip memory: 17 3 read-only 010 OCMEMn 32-bits wide #010 011 OCMEMn 64-bits wide #011 RO Read-Only 16 1 read-only 0 Writes to the OCMDRn[11:0] are allowed #0 1 Writes to the OCMDRn[11:0] are ignored #1 V OCMEM Valid bit. This read-only field defines the validity (presence) of the on-chip memory 31 1 read-only 0 OCMEMn is not present. #0 1 OCMEMn is present. #1 OCMDR1 On-Chip Memory Descriptor Register 0xC04 32 read-only n 0x0 0x0 OCMPU OCMEM Memory Protection Unit. This read-only field identifies a memory protected by an XRDC module. 12 1 read-only 0 OCMEMn is not protected by an XRDC module. #0 1 OCMEMn is protected by an XRDC module. #1 OCMSZ OCMEM Size 24 4 read-only 0000 no OCMEMn #0000 0100 4KB OCMEMn #0100 0101 8KB OCMEMn #0101 0110 16KB OCMEMn #0110 0111 32KB OCMEMn #0111 1111 8192KB OCMEMn #1111 OCMSZH OCMEM Size "Hole" 28 1 read-only 0 OCMEMn is a power-of-2 capacity. #0 1 OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. #1 OCMT OCMEM Type. This field defines the type of the on-chip memory: 13 3 read-only 000 OCMEMn is a system RAM. #000 001 OCMEMn is a graphics RAM. #001 011 OCMEMn is a ROM. #011 OCMW OCMEM datapath Width. This read-only field defines the width of the on-chip memory: 17 3 read-only 010 OCMEMn 32-bits wide #010 011 OCMEMn 64-bits wide #011 RO Read-Only 16 1 read-only 0 Writes to the OCMDRn[11:0] are allowed #0 1 Writes to the OCMDRn[11:0] are ignored #1 V OCMEM Valid bit. This read-only field defines the validity (presence) of the on-chip memory 31 1 read-only 0 OCMEMn is not present. #0 1 OCMEMn is present. #1 OCMDR2 On-Chip Memory Descriptor Register 0x100C 32 read-only n 0x0 0x0 OCMPU OCMEM Memory Protection Unit. This read-only field identifies a memory protected by an XRDC module. 12 1 read-only 0 OCMEMn is not protected by an XRDC module. #0 1 OCMEMn is protected by an XRDC module. #1 OCMSZ OCMEM Size 24 4 read-only 0000 no OCMEMn #0000 0100 4KB OCMEMn #0100 0101 8KB OCMEMn #0101 0110 16KB OCMEMn #0110 0111 32KB OCMEMn #0111 1111 8192KB OCMEMn #1111 OCMSZH OCMEM Size "Hole" 28 1 read-only 0 OCMEMn is a power-of-2 capacity. #0 1 OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. #1 OCMT OCMEM Type. This field defines the type of the on-chip memory: 13 3 read-only 000 OCMEMn is a system RAM. #000 001 OCMEMn is a graphics RAM. #001 011 OCMEMn is a ROM. #011 OCMW OCMEM datapath Width. This read-only field defines the width of the on-chip memory: 17 3 read-only 010 OCMEMn 32-bits wide #010 011 OCMEMn 64-bits wide #011 RO Read-Only 16 1 read-only 0 Writes to the OCMDRn[11:0] are allowed #0 1 Writes to the OCMDRn[11:0] are ignored #1 V OCMEM Valid bit. This read-only field defines the validity (presence) of the on-chip memory 31 1 read-only 0 OCMEMn is not present. #0 1 OCMEMn is present. #1 MTB0 Micro Trace Buffer MTB 0x0 0x0 0x1000 registers n AUTHSTAT Authentication Status Register 0xFB8 32 read-only n 0x0 0x0 BIT0 Connected to DBGEN. 0 1 read-only BIT1 BIT1 1 1 read-only BIT2 BIT2 2 1 read-only BIT3 BIT3 3 1 read-only BASE MTB Base Register 0xC 32 read-only n 0x0 0x0 BASEADDR BASEADDR 0 32 read-only COMPID0 Component ID Register 0x1FE0 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only COMPID1 Component ID Register 0x2FD4 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only COMPID2 Component ID Register 0x3FCC 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only COMPID3 Component ID Register 0x4FC8 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only DEVICEARCH Device Architecture Register 0xFBC 32 read-only n 0x0 0x0 DEVICEARCH DEVICEARCH 0 32 read-only DEVICECFG Device Configuration Register 0xFC8 32 read-only n 0x0 0x0 DEVICECFG DEVICECFG 0 32 read-only DEVICETYPID Device Type Identifier Register 0xFCC 32 read-only n 0x0 0x0 DEVICETYPID DEVICETYPID 0 32 read-only FLOW MTB Flow Register 0x8 32 read-write n 0x0 0x0 AUTOHALT AUTOHALT 1 1 read-write AUTOSTOP AUTOSTOP 0 1 read-write WATERMARK WATERMARK[28:0] 3 29 read-write LOCKACCESS Lock Access Register 0xFB0 32 read-only n 0x0 0x0 LOCKACCESS Hardwired to 0x0000_0000 0 32 read-only LOCKSTAT Lock Status Register 0xFB4 32 read-only n 0x0 0x0 LOCKSTAT LOCKSTAT 0 32 read-only MASTER MTB Master Register 0x4 32 read-write n 0x0 0x0 EN Main Trace Enable 31 1 read-write HALTREQ Halt Request 9 1 read-write MASK Mask 0 5 read-write RAMPRIV RAM Privilege 8 1 read-write SFRWPRIV Special Function Register Write Privilege 7 1 read-write TSTARTEN Trace Start Input Enable 5 1 read-write TSTOPEN Trace Stop Input Enable 6 1 read-write MODECTRL Integration Mode Control Register 0xF00 32 read-only n 0x0 0x0 MODECTRL MODECTRL 0 32 read-only PERIPHID0 Peripheral ID Register 0x5F08 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID1 Peripheral ID Register 0x6EEC 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID2 Peripheral ID Register 0x7ED4 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID3 Peripheral ID Register 0x8EC0 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID4 Peripheral ID Register 0x1FA0 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID5 Peripheral ID Register 0x2F74 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID6 Peripheral ID Register 0x3F4C 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID7 Peripheral ID Register 0x4F28 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only POSITION MTB Position Register 0x0 32 read-write n 0x0 0x0 POINTER Trace Packet Address Pointer[28:0] 3 29 read-write WRAP WRAP 2 1 read-write TAGCLEAR Claim TAG Clear Register 0xFA4 32 read-only n 0x0 0x0 TAGCLEAR TAGCLEAR 0 32 read-only TAGSET Claim TAG Set Register 0xFA0 32 read-only n 0x0 0x0 TAGSET TAGSET 0 32 read-only MTB0_DWT MTB data watchpoint and trace MTB0_DWT 0x0 0x0 0x1000 registers n COMP0 MTB_DWT Comparator Register 0x40 32 read-write n 0x0 0x0 COMP Reference value for comparison 0 32 read-write COMP1 MTB_DWT Comparator Register 0x70 32 read-write n 0x0 0x0 COMP Reference value for comparison 0 32 read-write COMPID0 Component ID Register 0x1FE0 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only COMPID1 Component ID Register 0x2FD4 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only COMPID2 Component ID Register 0x3FCC 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only COMPID3 Component ID Register 0x4FC8 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only CTRL MTB DWT Control Register 0x0 32 read-only n 0x0 0x0 DWTCFGCTRL DWT configuration controls 0 28 read-only NUMCMP Number of comparators 28 4 read-only DEVICECFG Device Configuration Register 0xFC8 32 read-only n 0x0 0x0 DEVICECFG DEVICECFG 0 32 read-only DEVICETYPID Device Type Identifier Register 0xFCC 32 read-only n 0x0 0x0 DEVICETYPID DEVICETYPID 0 32 read-only FCT0 MTB_DWT Comparator Function Register 0 0x28 32 read-write n 0x0 0x0 DATAVADDR0 Data Value Address 0 12 4 read-write DATAVMATCH Data Value Match 8 1 read-write 0 Perform address comparison. #0 1 Perform data value comparison. #1 DATAVSIZE Data Value Size 10 2 read-write 00 Byte. #00 01 Halfword. #01 10 Word. #10 11 Reserved. Any attempts to use this value results in UNPREDICTABLE behavior. #11 FUNCTION Function 0 4 read-write 0000 Disabled. #0000 0100 Instruction fetch. #0100 0101 Data operand read. #0101 0110 Data operand write. #0110 0111 Data operand (read + write). #0111 MATCHED Comparator match 24 1 read-only 0 No match. #0 1 Match occurred. #1 FCT1 MTB_DWT Comparator Function Register 1 0x38 32 read-write n 0x0 0x0 FUNCTION Function 0 4 read-write 0000 Disabled. #0000 0100 Instruction fetch. #0100 0101 Data operand read. #0101 0110 Data operand write. #0110 0111 Data operand (read + write). #0111 MATCHED Comparator match 24 1 read-only 0 No match. #0 1 Match occurred. #1 MASK0 MTB_DWT Comparator Mask Register 0x48 32 read-write n 0x0 0x0 MASK MASK 0 5 read-write MASK1 MTB_DWT Comparator Mask Register 0x7C 32 read-write n 0x0 0x0 MASK MASK 0 5 read-write PERIPHID0 Peripheral ID Register 0x5F08 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID1 Peripheral ID Register 0x6EEC 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID2 Peripheral ID Register 0x7ED4 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID3 Peripheral ID Register 0x8EC0 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID4 Peripheral ID Register 0x1FA0 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID5 Peripheral ID Register 0x2F74 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID6 Peripheral ID Register 0x3F4C 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID7 Peripheral ID Register 0x4F28 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only TBCTRL MTB_DWT Trace Buffer Control Register 0x200 32 read-write n 0x0 0x0 ACOMP0 Action based on Comparator 0 match 0 1 read-write 0 Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED]. #0 1 Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED]. #1 ACOMP1 Action based on Comparator 1 match 1 1 read-write 0 Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED]. #0 1 Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED]. #1 NUMCOMP Number of Comparators 28 4 read-only MTB0_ROM System ROM MTB0_ROM 0x0 0x0 0x1000 registers n COMPID0 Component ID Register 0x1FE0 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only COMPID1 Component ID Register 0x2FD4 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only COMPID2 Component ID Register 0x3FCC 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only COMPID3 Component ID Register 0x4FC8 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only ENTRY0 Entry 0x0 32 read-only n 0x0 0x0 ENTRY ENTRY 0 32 read-only ENTRY1 Entry 0x4 32 read-only n 0x0 0x0 ENTRY ENTRY 0 32 read-only ENTRY2 Entry 0xC 32 read-only n 0x0 0x0 ENTRY ENTRY 0 32 read-only ENTRY3 Entry 0x18 32 read-only n 0x0 0x0 ENTRY ENTRY 0 32 read-only PERIPHID0 Peripheral ID Register 0x5F08 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID1 Peripheral ID Register 0x6EEC 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID2 Peripheral ID Register 0x7ED4 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID3 Peripheral ID Register 0x8EC0 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID4 Peripheral ID Register 0x1FA0 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID5 Peripheral ID Register 0x2F74 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID6 Peripheral ID Register 0x3F4C 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID7 Peripheral ID Register 0x4F28 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only SYSACCESS System Access Register 0xFCC 32 read-only n 0x0 0x0 SYSACCESS SYSACCESS 0 32 read-only TABLEMARK End of Table Marker Register 0x10 32 read-only n 0x0 0x0 MARK MARK 0 32 read-only MTB1 Micro Trace Buffer MTB 0x0 0x0 0x1000 registers n AUTHSTAT Authentication Status Register 0xFB8 32 read-only n 0x0 0x0 BIT0 Connected to DBGEN. 0 1 read-only BIT1 BIT1 1 1 read-only BIT2 BIT2 2 1 read-only BIT3 BIT3 3 1 read-only BASE MTB Base Register 0xC 32 read-only n 0x0 0x0 BASEADDR BASEADDR 0 32 read-only COMPID0 Component ID Register 0x1FE0 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only COMPID1 Component ID Register 0x2FD4 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only COMPID2 Component ID Register 0x3FCC 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only COMPID3 Component ID Register 0x4FC8 32 read-only n 0x0 0x0 COMPID Component ID 0 32 read-only DEVICEARCH Device Architecture Register 0xFBC 32 read-only n 0x0 0x0 DEVICEARCH DEVICEARCH 0 32 read-only DEVICECFG Device Configuration Register 0xFC8 32 read-only n 0x0 0x0 DEVICECFG DEVICECFG 0 32 read-only DEVICETYPID Device Type Identifier Register 0xFCC 32 read-only n 0x0 0x0 DEVICETYPID DEVICETYPID 0 32 read-only FLOW MTB Flow Register 0x8 32 read-write n 0x0 0x0 AUTOHALT AUTOHALT 1 1 read-write AUTOSTOP AUTOSTOP 0 1 read-write WATERMARK WATERMARK[28:0] 3 29 read-write LOCKACCESS Lock Access Register 0xFB0 32 read-only n 0x0 0x0 LOCKACCESS Hardwired to 0x0000_0000 0 32 read-only LOCKSTAT Lock Status Register 0xFB4 32 read-only n 0x0 0x0 LOCKSTAT LOCKSTAT 0 32 read-only MASTER MTB Master Register 0x4 32 read-write n 0x0 0x0 EN Main Trace Enable 31 1 read-write HALTREQ Halt Request 9 1 read-write MASK Mask 0 5 read-write RAMPRIV RAM Privilege 8 1 read-write SFRWPRIV Special Function Register Write Privilege 7 1 read-write TSTARTEN Trace Start Input Enable 5 1 read-write TSTOPEN Trace Stop Input Enable 6 1 read-write MODECTRL Integration Mode Control Register 0xF00 32 read-only n 0x0 0x0 MODECTRL MODECTRL 0 32 read-only PERIPHID0 Peripheral ID Register 0x5F08 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID1 Peripheral ID Register 0x6EEC 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID2 Peripheral ID Register 0x7ED4 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID3 Peripheral ID Register 0x8EC0 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID4 Peripheral ID Register 0x1FA0 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID5 Peripheral ID Register 0x2F74 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID6 Peripheral ID Register 0x3F4C 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only PERIPHID7 Peripheral ID Register 0x4F28 32 read-only n 0x0 0x0 PERIPHID PERIPHID 0 32 read-only POSITION MTB Position Register 0x0 32 read-write n 0x0 0x0 POINTER Trace Packet Address Pointer[28:0] 3 29 read-write WRAP WRAP 2 1 read-write TAGCLEAR Claim TAG Clear Register 0xFA4 32 read-only n 0x0 0x0 TAGCLEAR TAGCLEAR 0 32 read-only TAGSET Claim TAG Set Register 0xFA0 32 read-only n 0x0 0x0 TAGSET TAGSET 0 32 read-only MU0_A MU MU 0x0 0x0 0x68 registers n MU0_A 16 CR Control Register 0x64 32 read-write n 0x0 0x0 BBOOT Processor B Boot Config. 9 2 read-write 00 Boot from 0x0 #00 01 Boot from DMEM Base #01 10 Boot from IMEM Base #10 BRSTH Processor B Reset Hold 7 1 read-write 0 Release Processor B from reset #0 1 Hold Processor B in reset #1 CLKE Processor B/A clock enable 8 1 read-write 0 Processor B/A platform clock gated when Processor B/A enters a stop mode. #0 1 Processor B/A platform clock kept running after Processor B/A enters a stop mode, until Processor A/B also enters a stop mode. #1 Fn For n = {0, 1, 2} Processor A/B to Processor B/A Flag n 0 3 read-write 0 Clears the Fn bit in the SR register. #000 1 Sets the Fn bit in the SR register. #001 GIEn For n = {0, 1, 2, 3} Processor A/B General Purpose Interrupt Enable n 28 4 read-write 0 Disables Processor A/B General Interrupt n. (default) #0000 1 Enables Processor A/B General Interrupt n. #0001 GIRn For n = {0, 1, 2, 3} Processor A/B General Purpose Interrupt Request n 16 4 read-write 0 Processor A/B General Interrupt n is not requested to the Processor B/A (default). #0000 1 Processor A/B General Interrupt n is requested to the Processor B/A. #0001 MUR Processor A MU Reset 5 1 read-write 0 N/A. Self clearing bit (default). #0 1 Asserts the Processor A MU reset. #1 NMI Processor B/A Non-maskable Interrupt 3 1 read-write 0 Non-maskable interrupt is not issued to the Processor B/A by the Processor A/B (default). #0 1 Non-maskable interrupt is issued to the Processor B/A by the Processor A/B. #1 RIEn For n = {0, 1, 2, 3} Processor A/B Receive Interrupt Enable n 24 4 read-write 0 Disables Processor A/B Receive Interrupt n. (default) #0000 1 Enables Processor A/B Receive Interrupt n. #0001 TIEn For n = {0, 1, 2, 3} Processor A/B Transmit Interrupt Enable n 20 4 read-write 0 Disables Processor A/B Transmit Interrupt n. (default) #0000 1 Enables Processor A/B Transmit Interrupt n. #0001 RR0 Receive Register 0x80 32 read-only n 0x0 0x0 DATA Processor A/B Receive Register 0 32 read-only RR1 Receive Register 0xC4 32 read-only n 0x0 0x0 DATA Processor A/B Receive Register 0 32 read-only RR2 Receive Register 0x10C 32 read-only n 0x0 0x0 DATA Processor A/B Receive Register 0 32 read-only RR3 Receive Register 0x158 32 read-only n 0x0 0x0 DATA Processor A/B Receive Register 0 32 read-only SR Status Register 0x60 32 read-write n 0x0 0x0 EP Processor A/B Side Event Pending 4 1 read-write 0 The Processor A-side event is not pending (default). #0 1 The Processor A-side event is pending. #1 Fn For n = {0, 1, 2} Processor A/B Side Flag n 0 3 read-write 0 Processor B/A Fn bit in the CR register is written 0 (default). #000 1 Processor B/A Fn bit in the CR register is written 1. #001 FUP Processor A/B Flags Update Pending 8 1 read-write 0 No flags updated, initiated by the Processor A, in progress (default) #0 1 Processor A/B initiated flags update, processing #1 GIPn For n = {0, 1, 2, 3} Processor A/B General Interrupt Request n Pending 28 4 read-write 0 Processor A/B general purpose interrupt n is not pending. (default) #0000 1 Processor A/B general purpose interrupt n is pending. #0001 NMIC Processor A/B Non-Maskable-Interrupt Clear 3 1 read-write 0 Default #0 1 Writing "1" clears the NMI bit in the BCR register. #1 PM Processor B/A Power Mode 5 2 read-write 00 The Processor B/A is in Run Mode. #00 01 The Processor B/A is in WAIT Mode. #01 10 The Processor B/A is in STOP/VLPS Mode. #10 11 The Processor B/A is in LLS/VLLS Mode. #11 RFn For n = {0, 1, 2, 3} Processor A/B Receive Register n Full 24 4 read-write 0 Processor A/B RRn register is not full (default). #0000 1 Processor A/B RRn register has received data from Processor B/A TRn register and is ready to be read by the Processor A/B. #0001 TEn For n = {0, 1, 2, 3} Processor A/B Transmit Register n Empty 20 4 read-write 0 Processor A/B TRn register is not empty. #0000 1 Processor A/B TRn register is empty (default). #0001 TR0 Transmit Register 0x40 32 read-write n 0x0 0x0 DATA Processor A/B Transmit Register Data 0 32 read-write TR1 Transmit Register 0x64 32 read-write n 0x0 0x0 DATA Processor A/B Transmit Register Data 0 32 read-write TR2 Transmit Register 0x8C 32 read-write n 0x0 0x0 DATA Processor A/B Transmit Register Data 0 32 read-write TR3 Transmit Register 0xB8 32 read-write n 0x0 0x0 DATA Processor A/B Transmit Register Data 0 32 read-write VER Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Specification Number 0 16 read-only 0 TBD #0 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only MU0_B MU MU 0x0 0x0 0x68 registers n CR Control Register 0x64 32 read-write n 0x0 0x0 BBOOT Processor B Boot Config. 9 2 read-write 00 Boot from 0x0 #00 01 Boot from DMEM Base #01 10 Boot from IMEM Base #10 BRSTH Processor B Reset Hold 7 1 read-write 0 Release Processor B from reset #0 1 Hold Processor B in reset #1 CLKE Processor B/A clock enable 8 1 read-write 0 Processor B/A platform clock gated when Processor B/A enters a stop mode. #0 1 Processor B/A platform clock kept running after Processor B/A enters a stop mode, until Processor A/B also enters a stop mode. #1 Fn For n = {0, 1, 2} Processor A/B to Processor B/A Flag n 0 3 read-write 0 Clears the Fn bit in the SR register. #000 1 Sets the Fn bit in the SR register. #001 GIEn For n = {0, 1, 2, 3} Processor A/B General Purpose Interrupt Enable n 28 4 read-write 0 Disables Processor A/B General Interrupt n. (default) #0000 1 Enables Processor A/B General Interrupt n. #0001 GIRn For n = {0, 1, 2, 3} Processor A/B General Purpose Interrupt Request n 16 4 read-write 0 Processor A/B General Interrupt n is not requested to the Processor B/A (default). #0000 1 Processor A/B General Interrupt n is requested to the Processor B/A. #0001 MUR Processor A MU Reset 5 1 read-write 0 N/A. Self clearing bit (default). #0 1 Asserts the Processor A MU reset. #1 NMI Processor B/A Non-maskable Interrupt 3 1 read-write 0 Non-maskable interrupt is not issued to the Processor B/A by the Processor A/B (default). #0 1 Non-maskable interrupt is issued to the Processor B/A by the Processor A/B. #1 RIEn For n = {0, 1, 2, 3} Processor A/B Receive Interrupt Enable n 24 4 read-write 0 Disables Processor A/B Receive Interrupt n. (default) #0000 1 Enables Processor A/B Receive Interrupt n. #0001 TIEn For n = {0, 1, 2, 3} Processor A/B Transmit Interrupt Enable n 20 4 read-write 0 Disables Processor A/B Transmit Interrupt n. (default) #0000 1 Enables Processor A/B Transmit Interrupt n. #0001 RR0 Receive Register 0x80 32 read-only n 0x0 0x0 DATA Processor A/B Receive Register 0 32 read-only RR1 Receive Register 0xC4 32 read-only n 0x0 0x0 DATA Processor A/B Receive Register 0 32 read-only RR2 Receive Register 0x10C 32 read-only n 0x0 0x0 DATA Processor A/B Receive Register 0 32 read-only RR3 Receive Register 0x158 32 read-only n 0x0 0x0 DATA Processor A/B Receive Register 0 32 read-only SR Status Register 0x60 32 read-write n 0x0 0x0 EP Processor A/B Side Event Pending 4 1 read-write 0 The Processor A-side event is not pending (default). #0 1 The Processor A-side event is pending. #1 Fn For n = {0, 1, 2} Processor A/B Side Flag n 0 3 read-write 0 Processor B/A Fn bit in the CR register is written 0 (default). #000 1 Processor B/A Fn bit in the CR register is written 1. #001 FUP Processor A/B Flags Update Pending 8 1 read-write 0 No flags updated, initiated by the Processor A, in progress (default) #0 1 Processor A/B initiated flags update, processing #1 GIPn For n = {0, 1, 2, 3} Processor A/B General Interrupt Request n Pending 28 4 read-write 0 Processor A/B general purpose interrupt n is not pending. (default) #0000 1 Processor A/B general purpose interrupt n is pending. #0001 NMIC Processor A/B Non-Maskable-Interrupt Clear 3 1 read-write 0 Default #0 1 Writing "1" clears the NMI bit in the BCR register. #1 PM Processor B/A Power Mode 5 2 read-write 00 The Processor B/A is in Run Mode. #00 01 The Processor B/A is in WAIT Mode. #01 10 The Processor B/A is in STOP/VLPS Mode. #10 11 The Processor B/A is in LLS/VLLS Mode. #11 RFn For n = {0, 1, 2, 3} Processor A/B Receive Register n Full 24 4 read-write 0 Processor A/B RRn register is not full (default). #0000 1 Processor A/B RRn register has received data from Processor B/A TRn register and is ready to be read by the Processor A/B. #0001 TEn For n = {0, 1, 2, 3} Processor A/B Transmit Register n Empty 20 4 read-write 0 Processor A/B TRn register is not empty. #0000 1 Processor A/B TRn register is empty (default). #0001 TR0 Transmit Register 0x40 32 read-write n 0x0 0x0 DATA Processor A/B Transmit Register Data 0 32 read-write TR1 Transmit Register 0x64 32 read-write n 0x0 0x0 DATA Processor A/B Transmit Register Data 0 32 read-write TR2 Transmit Register 0x8C 32 read-write n 0x0 0x0 DATA Processor A/B Transmit Register Data 0 32 read-write TR3 Transmit Register 0xB8 32 read-write n 0x0 0x0 DATA Processor A/B Transmit Register Data 0 32 read-write VER Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Specification Number 0 16 read-only 0 TBD #0 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only PCC0 PCC-0 PCC 0x0 0x20 0x1C4 registers n PCC_ADC0 PCC CLKCFG Register 0x198 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off (or test clock is enabled). #000 1 OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk). #001 2 SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz). #010 3 SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz). #011 6 SCGPCLK System PLL clock (scg_spll_slow_clk). #110 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_CMP0 PCC CLKCFG Register 0x1B8 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_CRC PCC CLKCFG Register 0x1E0 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_DAC0 PCC CLKCFG Register 0x1A8 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_DMA0 PCC CLKCFG Register 0x20 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_DMAMUX0 PCC CLKCFG Register 0x84 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_EMVSIM0 PCC CLKCFG Register 0x138 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off (or test clock is enabled). #000 1 OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk). #001 2 SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz). #010 3 SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz). #011 6 SCGPCLK System PLL clock (scg_spll_slow_clk). #110 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_FLASH PCC CLKCFG Register 0x80 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_INTMUX0 PCC CLKCFG Register 0x90 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_LPI2C2 PCC CLKCFG Register 0x108 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off (or test clock is enabled). #000 1 OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk). #001 2 SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz). #010 3 SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz). #011 6 SCGPCLK System PLL clock (scg_spll_slow_clk). #110 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_LPIT0 PCC CLKCFG Register 0xC0 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off (or test clock is enabled). #000 1 OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk). #001 2 SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz). #010 3 SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz). #011 6 SCGPCLK System PLL clock (scg_spll_slow_clk). #110 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_LPSPI2 PCC CLKCFG Register 0xF8 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off (or test clock is enabled). #000 1 OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk). #001 2 SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz). #010 3 SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz). #011 6 SCGPCLK System PLL clock (scg_spll_slow_clk). #110 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_LPTMR0 PCC CLKCFG Register 0xD0 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_LPUART2 PCC CLKCFG Register 0x118 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off (or test clock is enabled). #000 1 OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk). #001 2 SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz). #010 3 SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz). #011 6 SCGPCLK System PLL clock (scg_spll_slow_clk). #110 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_MU0_A PCC CLKCFG Register 0x8C 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_PORTA PCC CLKCFG Register 0x168 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_PORTB PCC CLKCFG Register 0x16C 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_PORTC PCC CLKCFG Register 0x170 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_PORTD PCC CLKCFG Register 0x174 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_PORTE PCC CLKCFG Register 0x178 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_RTC PCC CLKCFG Register 0xE0 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_SAI0 PCC CLKCFG Register 0x130 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off (or test clock is enabled) An external clock can be enabled for this peripheral. #000 1 OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk). #001 2 SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz). #010 3 SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz). #011 6 SCGPCLK System PLL clock (scg_spll_slow_clk). #110 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_SEMA42_0 PCC CLKCFG Register 0x6C 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_TPM2 PCC CLKCFG Register 0xB8 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off (or test clock is enabled). #000 1 OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk). #001 2 SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz). #010 3 SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz). #011 6 SCGPCLK System PLL clock (scg_spll_slow_clk). #110 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_TSI0 PCC CLKCFG Register 0x188 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_USB0FS PCC CLKCFG Register 0x154 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 FRAC Peripheral Clock Divider Fraction 3 1 read-write 0 Fractional value is 0. #0 1 Fractional value is 1. #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PCD Peripheral Clock Divider Select 0 3 read-write 0 Divide by 1 (pass-through, no clock divide). #000 1 Divide by 2. #001 2 Divide by 3. #010 3 Divide by 4. #011 4 Divide by 5. #100 5 Divide by 6. #101 6 Divide by 7. #110 7 Divide by 8. #111 PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off (or test clock is enabled) An external clock can be enabled for this peripheral. #000 1 OSCCLK - System Oscillator Platform Clock(scg_sosc_plat_clk). #001 2 SCGIRCLK - Slow IRC Clock(scg_sirc_plat_clk), (maximum is 8MHz). #010 3 SCGFIRCLK - Fast IRC Clock(scg_firc_plat_clk), (maximum is 48MHz). #011 6 SCGPCLK System PLL clock (scg_spll_plat_clk). #110 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_VREF PCC CLKCFG Register 0x1C8 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_XRDC PCC CLKCFG Register 0x50 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC1 PCC-1 PCC 0x0 0x20 0x1A0 registers n PCC_CMP1 PCC CLKCFG Register 0x1BC 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_DMA1 PCC CLKCFG Register 0x20 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_DMAMUX1 PCC CLKCFG Register 0x84 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_FLEXIO0 PCC CLKCFG Register 0x128 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off (or test clock is enabled). #000 1 OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk). #001 2 SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz). #010 3 SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz). #011 6 SCGPCLK System PLL clock (scg_spll_slow_clk). #110 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_INTMUX1 PCC CLKCFG Register 0x90 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_LPI2C0 PCC CLKCFG Register 0x100 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off (or test clock is enabled). #000 1 OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk). #001 2 SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz). #010 3 SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz). #011 6 SCGPCLK System PLL clock (scg_spll_slow_clk). #110 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_LPI2C1 PCC CLKCFG Register 0x104 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off (or test clock is enabled). #000 1 OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk). #001 2 SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz). #010 3 SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz). #011 6 SCGPCLK System PLL clock (scg_spll_slow_clk). #110 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_LPIT1 PCC CLKCFG Register 0xC4 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off (or test clock is enabled). #000 1 OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk). #001 2 SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz). #010 3 SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz). #011 6 SCGPCLK System PLL clock (scg_spll_slow_clk). #110 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_LPSPI0 PCC CLKCFG Register 0xF0 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off (or test clock is enabled). #000 1 OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk). #001 2 SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz). #010 3 SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz). #011 6 SCGPCLK System PLL clock (scg_spll_slow_clk). #110 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_LPSPI1 PCC CLKCFG Register 0xF4 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off (or test clock is enabled). #000 1 OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk). #001 2 SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz). #010 3 SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz). #011 6 SCGPCLK System PLL clock (scg_spll_slow_clk). #110 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_LPTMR1 PCC CLKCFG Register 0xD4 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_LPUART0 PCC CLKCFG Register 0x110 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off (or test clock is enabled). #000 1 OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk). #001 2 SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz). #010 3 SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz). #011 6 SCGPCLK System PLL clock (scg_spll_slow_clk). #110 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_LPUART1 PCC CLKCFG Register 0x114 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off (or test clock is enabled). #000 1 OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk). #001 2 SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz). #010 3 SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz). #011 6 SCGPCLK System PLL clock (scg_spll_slow_clk). #110 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_MU0_B PCC CLKCFG Register 0x8C 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_PORTM PCC CLKCFG Register 0x180 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_SEMA42_1 PCC CLKCFG Register 0x6C 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_TPM0 PCC CLKCFG Register 0xB0 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off (or test clock is enabled). #000 1 OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk). #001 2 SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz). #010 3 SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz). #011 6 SCGPCLK System PLL clock (scg_spll_slow_clk). #110 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_TPM1 PCC CLKCFG Register 0xB4 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PCS Peripheral Clock Source Select 24 3 read-write 000 Clock is off (or test clock is enabled). #000 1 OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk). #001 2 SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz). #010 3 SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz). #011 6 SCGPCLK System PLL clock (scg_spll_slow_clk). #110 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PCC_TRNG PCC CLKCFG Register 0x94 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write 0 Clock disabled #0 1 Clock enabled #1 INUSE Clock Gate Control 29 1 read-only 0 Another core is not using this peripheral. #0 1 Another core is using this peripheral. Software cannot modify the existing clocking configuration. #1 PR Enable 31 1 read-only 0 Peripheral is not present. #0 1 Peripheral is present. #1 PMC Power Management Controller PMC 0x0 0x0 0x38 registers n PMC 41 HVDSC1 High Voltage Detect Status And Control 1 register 0x34 32 read-write n 0x0 0x0 HVDACK High-Voltage Detect Acknowledge 6 1 write-only HVDF High-Voltage Detect Flag 7 1 read-only 0 High-voltage event not detected #0 1 High-voltage event detected #1 HVDIE High-Voltage Detect Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling) #0 1 Request a hardware interrupt when HVDF = 1 #1 HVDRE High-Voltage Detect Reset Enable 4 1 read-write 0 HVDF does not generate hardware resets #0 1 Force an MCU reset when HVDF = 1 #1 HVDV High-Voltage Detect Voltage Select 0 1 read-write 0 Low trip point selected (V HVD = V HVDL ) #0 1 High trip point selected (V HVD = V HVDH ) #1 LVDSC1 Low Voltage Detect Status And Control 1 register 0x8 32 read-write n 0x0 0x0 LVDACK Low-Voltage Detect Acknowledge 6 1 write-only LVDF Low-Voltage Detect Flag 7 1 read-only 0 Low-voltage event not detected #0 1 Low-voltage event detected #1 LVDIE Low-Voltage Detect Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling) #0 1 Request a hardware interrupt when LVDF = 1 #1 LVDRE Low-Voltage Detect Reset Enable 4 1 read-write 0 LVDF does not generate hardware resets #0 1 Force an MCU reset when LVDF = 1 #1 LVDV Low-Voltage Detect Voltage Select 0 2 read-write 00 Low trip point selected (V LVD = V LVDL ) #00 01 High trip point selected (V LVD = V LVDH ) #01 LVDSC2 Low Voltage Detect Status And Control 2 register 0xC 32 read-write n 0x0 0x0 LVWACK Low-Voltage Warning Acknowledge 6 1 write-only LVWF Low-Voltage Warning Flag 7 1 read-only 0 Low-voltage warning event not detected #0 1 Low-voltage warning event detected #1 LVWIE Low-Voltage Warning Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling) #0 1 Request a hardware interrupt when LVWF = 1 #1 LVWV Low-Voltage Warning Voltage Select 0 2 read-write 00 Low trip point selected (VLVW = VLVW1) #00 01 Mid 1 trip point selected (VLVW = VLVW2) #01 10 Mid 2 trip point selected (VLVW = VLVW3) #10 11 High trip point selected (VLVW = VLVW4) #11 PARAM Parameter register 0x4 32 read-only n 0x0 0x0 HVDE HVD Enabled 1 1 read-only VLPOE VLPO Enable 0 1 read-only REGSC Regulator Status And Control register 0x10 32 read-write n 0x0 0x0 ACKISO Acknowledge Isolation 3 1 read-write 0 Peripherals and I/O pads are in normal run state. #0 1 Certain peripherals and I/O pads are in an isolated and latched state. #1 BGBE Bandgap Buffer Enable 0 1 read-write 0 Bandgap buffer not enabled #0 1 Bandgap buffer enabled #1 BGEN Bandgap Enable In VLPx Operation 4 1 read-write 0 Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes. #0 1 Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes. #1 REGONS Regulator In Run Regulation Status 2 1 read-only 0 Regulator is in stop regulation or in transition to/from it #0 1 Regulator is in run regulation #1 VLPO VLPx Option 6 1 read-write 0 Operating frequencies and SCG clocking modes are restricted during VLPx modes as listed in the Power Management chapter. #0 1 If BGEN is also set, operating frequencies and SCG clocking modes are unrestricted during VLPx modes. Note that flash access frequency is still restricted however. #1 VERID Version ID register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Specification Number 0 16 read-only 0 Standard features implemented #0 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only PORTA Pin Control and Interrupts PORT 0x0 0x0 0xCC registers n PORTA 17 DFCR Digital Filter Clock Register 0xC4 32 read-write n 0x0 0x0 CS Clock Source 0 1 read-write 0 Digital filters are clocked by the bus clock. #0 1 Digital filters are clocked by the LPO clock. #1 DFER Digital Filter Enable Register 0xC0 32 read-write n 0x0 0x0 DFE Digital Filter Enable 0 32 read-write 0 Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. #0 1 Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DFWR Digital Filter Width Register 0xC8 32 read-write n 0x0 0x0 FILT Filter Length 0 5 read-write GICHR Global Interrupt Control High Register 0x8C 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GICLR Global Interrupt Control Low Register 0x88 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR0 Pin Control Register n 0x0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR1 Pin Control Register n 0x4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR10 Pin Control Register n 0x28 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR11 Pin Control Register n 0x2C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR12 Pin Control Register n 0x30 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR13 Pin Control Register n 0x34 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR14 Pin Control Register n 0x38 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR15 Pin Control Register n 0x3C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR16 Pin Control Register n 0x40 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR17 Pin Control Register n 0x44 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR18 Pin Control Register n 0x48 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR19 Pin Control Register n 0x4C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR2 Pin Control Register n 0x8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR20 Pin Control Register n 0x50 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR21 Pin Control Register n 0x54 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR22 Pin Control Register n 0x58 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR23 Pin Control Register n 0x5C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR24 Pin Control Register n 0x60 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR25 Pin Control Register n 0x64 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR26 Pin Control Register n 0x68 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR27 Pin Control Register n 0x6C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR28 Pin Control Register n 0x70 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR29 Pin Control Register n 0x74 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR3 Pin Control Register n 0xC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR30 Pin Control Register n 0x78 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR31 Pin Control Register n 0x7C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR4 Pin Control Register n 0x10 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR5 Pin Control Register n 0x14 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR6 Pin Control Register n 0x18 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR7 Pin Control Register n 0x1C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR8 Pin Control Register n 0x20 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR9 Pin Control Register n 0x24 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PORTB Pin Control and Interrupts PORT 0x0 0x0 0xCC registers n PORTB 18 DFCR Digital Filter Clock Register 0xC4 32 read-write n 0x0 0x0 CS Clock Source 0 1 read-write 0 Digital filters are clocked by the bus clock. #0 1 Digital filters are clocked by the LPO clock. #1 DFER Digital Filter Enable Register 0xC0 32 read-write n 0x0 0x0 DFE Digital Filter Enable 0 32 read-write 0 Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. #0 1 Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DFWR Digital Filter Width Register 0xC8 32 read-write n 0x0 0x0 FILT Filter Length 0 5 read-write GICHR Global Interrupt Control High Register 0x8C 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GICLR Global Interrupt Control Low Register 0x88 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR0 Pin Control Register n 0x0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR1 Pin Control Register n 0x4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR10 Pin Control Register n 0x28 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR11 Pin Control Register n 0x2C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR12 Pin Control Register n 0x30 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR13 Pin Control Register n 0x34 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR14 Pin Control Register n 0x38 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR15 Pin Control Register n 0x3C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR16 Pin Control Register n 0x40 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR17 Pin Control Register n 0x44 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR18 Pin Control Register n 0x48 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR19 Pin Control Register n 0x4C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR2 Pin Control Register n 0x8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR20 Pin Control Register n 0x50 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR21 Pin Control Register n 0x54 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR22 Pin Control Register n 0x58 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR23 Pin Control Register n 0x5C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR24 Pin Control Register n 0x60 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR25 Pin Control Register n 0x64 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR26 Pin Control Register n 0x68 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR27 Pin Control Register n 0x6C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR28 Pin Control Register n 0x70 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR29 Pin Control Register n 0x74 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR3 Pin Control Register n 0xC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR30 Pin Control Register n 0x78 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR31 Pin Control Register n 0x7C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR4 Pin Control Register n 0x10 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR5 Pin Control Register n 0x14 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR6 Pin Control Register n 0x18 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR7 Pin Control Register n 0x1C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR8 Pin Control Register n 0x20 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR9 Pin Control Register n 0x24 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PORTC Pin Control and Interrupts PORT 0x0 0x0 0xCC registers n PORTC 19 DFCR Digital Filter Clock Register 0xC4 32 read-write n 0x0 0x0 CS Clock Source 0 1 read-write 0 Digital filters are clocked by the bus clock. #0 1 Digital filters are clocked by the LPO clock. #1 DFER Digital Filter Enable Register 0xC0 32 read-write n 0x0 0x0 DFE Digital Filter Enable 0 32 read-write 0 Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. #0 1 Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DFWR Digital Filter Width Register 0xC8 32 read-write n 0x0 0x0 FILT Filter Length 0 5 read-write GICHR Global Interrupt Control High Register 0x8C 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GICLR Global Interrupt Control Low Register 0x88 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR0 Pin Control Register n 0x0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR1 Pin Control Register n 0x4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR10 Pin Control Register n 0x28 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR11 Pin Control Register n 0x2C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR12 Pin Control Register n 0x30 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR13 Pin Control Register n 0x34 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR14 Pin Control Register n 0x38 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR15 Pin Control Register n 0x3C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR16 Pin Control Register n 0x40 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR17 Pin Control Register n 0x44 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR18 Pin Control Register n 0x48 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR19 Pin Control Register n 0x4C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR2 Pin Control Register n 0x8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR20 Pin Control Register n 0x50 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR21 Pin Control Register n 0x54 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR22 Pin Control Register n 0x58 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR23 Pin Control Register n 0x5C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR24 Pin Control Register n 0x60 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR25 Pin Control Register n 0x64 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR26 Pin Control Register n 0x68 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR27 Pin Control Register n 0x6C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR28 Pin Control Register n 0x70 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR29 Pin Control Register n 0x74 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR3 Pin Control Register n 0xC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR30 Pin Control Register n 0x78 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR31 Pin Control Register n 0x7C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR4 Pin Control Register n 0x10 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR5 Pin Control Register n 0x14 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR6 Pin Control Register n 0x18 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR7 Pin Control Register n 0x1C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR8 Pin Control Register n 0x20 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR9 Pin Control Register n 0x24 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PORTD Pin Control and Interrupts PORT 0x0 0x0 0xCC registers n PORTD 20 DFCR Digital Filter Clock Register 0xC4 32 read-write n 0x0 0x0 CS Clock Source 0 1 read-write 0 Digital filters are clocked by the bus clock. #0 1 Digital filters are clocked by the LPO clock. #1 DFER Digital Filter Enable Register 0xC0 32 read-write n 0x0 0x0 DFE Digital Filter Enable 0 32 read-write 0 Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. #0 1 Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DFWR Digital Filter Width Register 0xC8 32 read-write n 0x0 0x0 FILT Filter Length 0 5 read-write GICHR Global Interrupt Control High Register 0x8C 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GICLR Global Interrupt Control Low Register 0x88 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR0 Pin Control Register n 0x0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR1 Pin Control Register n 0x4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR10 Pin Control Register n 0x28 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR11 Pin Control Register n 0x2C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR12 Pin Control Register n 0x30 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR13 Pin Control Register n 0x34 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR14 Pin Control Register n 0x38 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR15 Pin Control Register n 0x3C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR16 Pin Control Register n 0x40 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR17 Pin Control Register n 0x44 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR18 Pin Control Register n 0x48 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR19 Pin Control Register n 0x4C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR2 Pin Control Register n 0x8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR20 Pin Control Register n 0x50 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR21 Pin Control Register n 0x54 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR22 Pin Control Register n 0x58 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR23 Pin Control Register n 0x5C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR24 Pin Control Register n 0x60 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR25 Pin Control Register n 0x64 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR26 Pin Control Register n 0x68 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR27 Pin Control Register n 0x6C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR28 Pin Control Register n 0x70 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR29 Pin Control Register n 0x74 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR3 Pin Control Register n 0xC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR30 Pin Control Register n 0x78 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR31 Pin Control Register n 0x7C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR4 Pin Control Register n 0x10 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR5 Pin Control Register n 0x14 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR6 Pin Control Register n 0x18 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR7 Pin Control Register n 0x1C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR8 Pin Control Register n 0x20 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR9 Pin Control Register n 0x24 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PORTE Pin Control and Interrupts PORT 0x0 0x0 0xCC registers n PORTE 21 DFCR Digital Filter Clock Register 0xC4 32 read-write n 0x0 0x0 CS Clock Source 0 1 read-write 0 Digital filters are clocked by the bus clock. #0 1 Digital filters are clocked by the LPO clock. #1 DFER Digital Filter Enable Register 0xC0 32 read-write n 0x0 0x0 DFE Digital Filter Enable 0 32 read-write 0 Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. #0 1 Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DFWR Digital Filter Width Register 0xC8 32 read-write n 0x0 0x0 FILT Filter Length 0 5 read-write GICHR Global Interrupt Control High Register 0x8C 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GICLR Global Interrupt Control Low Register 0x88 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR0 Pin Control Register n 0x0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR1 Pin Control Register n 0x4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR10 Pin Control Register n 0x28 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR11 Pin Control Register n 0x2C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR12 Pin Control Register n 0x30 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR13 Pin Control Register n 0x34 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR14 Pin Control Register n 0x38 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR15 Pin Control Register n 0x3C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR16 Pin Control Register n 0x40 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR17 Pin Control Register n 0x44 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR18 Pin Control Register n 0x48 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR19 Pin Control Register n 0x4C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR2 Pin Control Register n 0x8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR20 Pin Control Register n 0x50 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR21 Pin Control Register n 0x54 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR22 Pin Control Register n 0x58 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR23 Pin Control Register n 0x5C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR24 Pin Control Register n 0x60 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR25 Pin Control Register n 0x64 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR26 Pin Control Register n 0x68 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR27 Pin Control Register n 0x6C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR28 Pin Control Register n 0x70 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR29 Pin Control Register n 0x74 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR3 Pin Control Register n 0xC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR30 Pin Control Register n 0x78 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR31 Pin Control Register n 0x7C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR4 Pin Control Register n 0x10 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR5 Pin Control Register n 0x14 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR6 Pin Control Register n 0x18 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-write 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-write 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR7 Pin Control Register n 0x1C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR8 Pin Control Register n 0x20 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR9 Pin Control Register n 0x24 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PORTM Pin Control and Interrupts PORT 0x0 0x0 0xCC registers n PORTM 51 DFCR Digital Filter Clock Register 0xC4 32 read-write n 0x0 0x0 CS Clock Source 0 1 read-write 0 Digital filters are clocked by the bus clock. #0 1 Digital filters are clocked by the LPO clock. #1 DFER Digital Filter Enable Register 0xC0 32 read-write n 0x0 0x0 DFE Digital Filter Enable 0 32 read-write 0 Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. #0 1 Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. #1 DFWR Digital Filter Width Register 0xC8 32 read-write n 0x0 0x0 FILT Filter Length 0 5 read-write GICHR Global Interrupt Control High Register 0x8C 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GICLR Global Interrupt Control Low Register 0x88 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only 0 Corresponding Pin Control Register is not updated with the value in GPWD. #0 1 Corresponding Pin Control Register is updated with the value in GPWD. #1 ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 PCR0 Pin Control Register n 0x0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR1 Pin Control Register n 0x4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR10 Pin Control Register n 0x28 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR11 Pin Control Register n 0x2C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR12 Pin Control Register n 0x30 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR13 Pin Control Register n 0x34 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR14 Pin Control Register n 0x38 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR15 Pin Control Register n 0x3C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR16 Pin Control Register n 0x40 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR17 Pin Control Register n 0x44 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR18 Pin Control Register n 0x48 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR19 Pin Control Register n 0x4C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR2 Pin Control Register n 0x8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR20 Pin Control Register n 0x50 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR21 Pin Control Register n 0x54 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR22 Pin Control Register n 0x58 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR23 Pin Control Register n 0x5C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR24 Pin Control Register n 0x60 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR25 Pin Control Register n 0x64 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR26 Pin Control Register n 0x68 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR27 Pin Control Register n 0x6C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR28 Pin Control Register n 0x70 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR29 Pin Control Register n 0x74 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR3 Pin Control Register n 0xC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR30 Pin Control Register n 0x78 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR31 Pin Control Register n 0x7C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR4 Pin Control Register n 0x10 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR5 Pin Control Register n 0x14 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR6 Pin Control Register n 0x18 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR7 Pin Control Register n 0x1C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR8 Pin Control Register n 0x20 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 PCR9 Pin Control Register n 0x24 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-only 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt Status Flag (ISF) is disabled. #0000 0001 ISF flag and DMA request on rising edge. #0001 0010 ISF flag and DMA request on falling edge. #0010 0011 ISF flag and DMA request on either edge. #0011 0101 Flag sets on rising edge. #0101 0110 Flag sets on falling edge. #0110 0111 Flag sets on either edge. #0111 1000 ISF flag and Interrupt when logic 0. #1000 1001 ISF flag and Interrupt on rising-edge. #1001 1010 ISF flag and Interrupt on falling-edge. #1010 1011 ISF flag and Interrupt on either edge. #1011 1100 ISF flag and Interrupt when logic 1. #1100 1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)] #1101 1110 Enable active low trigger output, flag is disabled. #1110 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt is not detected. #0 1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. #1 MUX Pin Mux Control 8 3 read-write 000 Pin disabled (Alternative 0) (analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip-specific). #010 011 Alternative 3 (chip-specific). #011 100 Alternative 4 (chip-specific). #100 101 Alternative 5 (chip-specific). #101 110 Alternative 6 (chip-specific). #110 111 Alternative 7 (chip-specific). #111 ODE Open Drain Enable 5 1 read-only 0 Open drain output is disabled on the corresponding pin. #0 1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. #1 PE Pull Enable 1 1 read-only 0 Internal pullup or pulldown resistor is not enabled on the corresponding pin. #0 1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-only 0 Passive input filter is disabled on the corresponding pin. #0 1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. #1 PS Pull Select 0 1 read-only 0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. #0 1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. #1 SRE Slew Rate Enable 2 1 read-only 0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. #1 RCM Reset Control Module RCM 0x0 0x0 0x20 registers n RCM 47 FM Force Mode Register 0x14 32 read-write n 0x0 0x0 FORCEROM Force ROM Boot 1 2 read-write 00 No effect #00 01 Force boot from ROM with RCM_MR[1] set. #01 10 Force boot from ROM with RCM_MR[2] set. #10 11 Force boot from ROM with RCM_MR[2:1] set. #11 MR Mode Register 0x10 32 read-write n 0x0 0x0 BOOTROM Boot ROM Configuration 1 2 read-write 00 Boot from Flash #00 01 Boot from ROM due to BOOTCFG0 pin assertion / Reserved if no Boot pin #01 10 Boot form ROM due to FOPT[7] configuration #10 11 Boot from ROM due to both BOOTCFG0 pin assertion and FOPT[7] configuration #11 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 RSTSRC Reset Source 0 32 read-only 0 Reset source not implemented. #0 1 Reset source implemented. #1 RPC Reset Pin Control register 0xC 32 read-write n 0x0 0x0 RSTFLTSEL Reset Pin Filter Bus Clock Select 8 5 read-write RSTFLTSRW Reset Pin Filter Select in Run and Wait Modes 0 2 read-write 00 All filtering disabled #00 01 Bus clock filter enabled for normal operation #01 10 LPO clock filter enabled for normal operation #10 RSTFLTSS Reset Pin Filter Select in Stop Mode 2 1 read-write 0 All filtering disabled #0 1 LPO clock filter enabled #1 SRIE System Reset Interrupt Enable Register 0x1C 32 read-write n 0x0 0x0 CORE1 Core 1 Interrupt 16 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 DELAY Reset Delay Time 0 2 read-write 00 8 LPO cycles #00 01 32 LPO cycles #01 10 128 LPO cycles #10 11 512 LPO cycles #11 GIE Global Interrupt Enable 7 1 read-write 0 All interrupt sources disabled. #0 1 All interrupt sources enabled. #1 LOC Loss-of-Clock Interrupt 2 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 LOCKUP Core Lockup Interrupt 9 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 LOL Loss-of-Lock Interrupt 3 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 MDM_AP MDM-AP System Reset Request 11 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 PIN External Reset Pin Interrupt 6 1 read-write 0 Reset not caused by external reset pin #0 1 Reset caused by external reset pin #1 SACKERR Stop Acknowledge Error Interrupt 13 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 SW Software Interrupt 10 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 WDOG Watchdog Interrupt 5 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 SRS System Reset Status Register 0x8 32 read-only n 0x0 0x0 CORE1 Core 1 Reset 16 1 read-only 0 Reset not caused by Core 1 Reset Source. #0 1 Reset caused by Core 1 Reset Source. #1 LOC Loss-of-Clock Reset 2 1 read-only 0 Reset not caused by a loss of external clock. #0 1 Reset caused by a loss of external clock. #1 LOCKUP Core Lockup 9 1 read-only 0 Reset not caused by core LOCKUP event #0 1 Reset caused by core LOCKUP event #1 LOL Loss-of-Lock Reset 3 1 read-only 0 Reset not caused by a loss of lock in the PLL #0 1 Reset caused by a loss of lock in the PLL #1 LVD Low-Voltage Detect Reset or High-Voltage Detect Reset 1 1 read-only 0 Reset not caused by LVD trip, HVD trip or POR #0 1 Reset caused by LVD trip, HVD trip or POR #1 MDM_AP MDM-AP System Reset Request 11 1 read-only 0 Reset was not caused by host debugger system setting of the System Reset Request bit #0 1 Reset was caused by host debugger system setting of the System Reset Request bit #1 PIN External Reset Pin 6 1 read-only 0 Reset not caused by external reset pin #0 1 Reset caused by external reset pin #1 POR Power-On Reset 7 1 read-only 0 Reset not caused by POR #0 1 Reset caused by POR #1 SACKERR Stop Acknowledge Error 13 1 read-only 0 Reset not caused by peripheral failure to acknowledge attempt to enter stop mode #0 1 Reset caused by peripheral failure to acknowledge attempt to enter stop mode #1 SW Software 10 1 read-only 0 Reset not caused by software setting of SYSRESETREQ bit #0 1 Reset caused by software setting of SYSRESETREQ bit #1 WAKEUP VLLS Wakeup Reset 0 1 read-only 0 Reset not caused by wakeup from VLLS mode. #0 1 Reset caused by wakeup from VLLS mode. #1 WDOG Watchdog 5 1 read-only 0 Reset not caused by watchdog timeout #0 1 Reset caused by watchdog timeout #1 SSRS Sticky System Reset Status Register 0x18 32 read-write n 0x0 0x0 SCORE1 Sticky Core 1 Reset 16 1 read-write 0 Reset not caused by Core 1 Reset Source. #0 1 Reset caused by Core 1 Reset Source. #1 SLOC Sticky Loss-of-Clock Reset 2 1 read-write 0 Reset not caused by a loss of external clock. #0 1 Reset caused by a loss of external clock. #1 SLOCKUP Sticky Core Lockup 9 1 read-write 0 Reset not caused by core LOCKUP event #0 1 Reset caused by core LOCKUP event #1 SLOL Sticky Loss-of-Lock Reset 3 1 read-write 0 Reset not caused by a loss of lock in the PLL #0 1 Reset caused by a loss of lock in the PLL #1 SLVD Sticky Low-Voltage Detect Reset 1 1 read-write 0 Reset not caused by LVD trip or POR #0 1 Reset caused by LVD trip or POR #1 SMDM_AP Sticky MDM-AP System Reset Request 11 1 read-only 0 Reset was not caused by host debugger system setting of the System Reset Request bit #0 1 Reset was caused by host debugger system setting of the System Reset Request bit #1 SPIN Sticky External Reset Pin 6 1 read-write 0 Reset not caused by external reset pin #0 1 Reset caused by external reset pin #1 SPOR Sticky Power-On Reset 7 1 read-write 0 Reset not caused by POR #0 1 Reset caused by POR #1 SSACKERR Sticky Stop Acknowledge Error 13 1 read-write 0 Reset not caused by peripheral failure to acknowledge attempt to enter stop mode #0 1 Reset caused by peripheral failure to acknowledge attempt to enter stop mode #1 SSW Sticky Software 10 1 read-write 0 Reset not caused by software setting of SYSRESETREQ bit #0 1 Reset caused by software setting of SYSRESETREQ bit #1 SWAKEUP Sticky VLLS Wakeup Reset 0 1 read-write 0 Reset not caused by wakeup from VLLS mode. #0 1 Reset caused by wakeup from VLLS mode. #1 SWDOG Sticky Watchdog 5 1 read-write 0 Reset not caused by watchdog timeout #0 1 Reset caused by watchdog timeout #1 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Specification Number 0 16 read-only 11 Standard feature set. #11 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only RFSYS System register file RFSYS 0x0 0x0 0x20 registers n REG0 Register file register 0x0 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG1 Register file register 0x4 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG2 Register file register 0xC 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG3 Register file register 0x18 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG4 Register file register 0x28 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG5 Register file register 0x3C 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG6 Register file register 0x54 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write REG7 Register file register 0x70 32 read-write n 0x0 0x0 HH High higher byte 24 8 read-write HL High lower byte 16 8 read-write LH Low higher byte 8 8 read-write LL Low lower byte 0 8 read-write RTC Secure Real Time Clock RTC 0x0 0x0 0x20 registers n RTC_Seconds 27 RTC 50 CR RTC Control Register 0x10 32 read-write n 0x0 0x0 CLKO Clock Output 9 1 read-write 0 The 32 kHz clock is output to other peripherals. #0 1 The 32 kHz clock is not output to other peripherals. #1 CPE Clock Pin Enable 24 2 read-write 00 RTC_CLKOUT is disabled. #00 01 RTC_CLKOUT is enabled on pin PTE0. #01 10 RTC_CLKOUT is enabled on pin PTE26. #10 CPS Clock Pin Select 5 1 read-write 0 The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT. #0 1 The RTC 32kHz crystal clock is output on RTC_CLKOUT. #1 LPOS LPO Select 7 1 read-write 0 RTC prescaler increments using 32kHz crystal. #0 1 RTC prescaler increments using 1kHz LPO, bits [4:0] of the prescaler are bypassed. #1 OSCE Oscillator Enable 8 1 read-write 0 32.768 kHz oscillator is disabled. #0 1 32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize. #1 SC16P Oscillator 16pF Load Configure 10 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SC2P Oscillator 2pF Load Configure 13 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SC4P Oscillator 4pF Load Configure 12 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SC8P Oscillator 8pF Load Configure 11 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SUP Supervisor Access 2 1 read-write 0 Non-supervisor mode write accesses are not supported and generate a bus error. #0 1 Non-supervisor mode write accesses are supported. #1 SWR Software Reset 0 1 read-write 0 No effect. #0 1 Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it. #1 UM Update Mode 3 1 read-write 0 Registers cannot be written when locked. #0 1 Registers can be written when locked under limited conditions. #1 WPE Wakeup Pin Enable 1 1 read-write 0 Wakeup pin is disabled. #0 1 Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on. #1 WPS Wakeup Pin Select 4 1 read-write 0 Wakeup pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on. #0 1 Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals. #1 IER RTC Interrupt Enable Register 0x1C 32 read-write n 0x0 0x0 TAIE Time Alarm Interrupt Enable 2 1 read-write 0 Time alarm flag does not generate an interrupt. #0 1 Time alarm flag does generate an interrupt. #1 TIIE Time Invalid Interrupt Enable 0 1 read-write 0 Time invalid flag does not generate an interrupt. #0 1 Time invalid flag does generate an interrupt. #1 TOIE Time Overflow Interrupt Enable 1 1 read-write 0 Time overflow flag does not generate an interrupt. #0 1 Time overflow flag does generate an interrupt. #1 TSIC Timer Seconds Interrupt Configuration 16 3 read-write 000 1 Hz. #000 001 2 Hz. #001 010 4 Hz. #010 011 8 Hz. #011 100 16 Hz. #100 101 32 Hz. #101 110 64 Hz. #110 111 128 Hz. #111 TSIE Time Seconds Interrupt Enable 4 1 read-write 0 Seconds interrupt is disabled. #0 1 Seconds interrupt is enabled. #1 WPON Wakeup Pin On 7 1 read-write 0 No effect. #0 1 If the wakeup pin is enabled, then the wakeup pin will assert. #1 LR RTC Lock Register 0x18 32 read-write n 0x0 0x0 CRL Control Register Lock 4 1 read-write 0 Control Register is locked and writes are ignored. #0 1 Control Register is not locked and writes complete as normal. #1 LRL Lock Register Lock 6 1 read-write 0 Lock Register is locked and writes are ignored. #0 1 Lock Register is not locked and writes complete as normal. #1 SRL Status Register Lock 5 1 read-write 0 Status Register is locked and writes are ignored. #0 1 Status Register is not locked and writes complete as normal. #1 TCL Time Compensation Lock 3 1 read-write 0 Time Compensation Register is locked and writes are ignored. #0 1 Time Compensation Register is not locked and writes complete as normal. #1 SR RTC Status Register 0x14 32 read-write n 0x0 0x0 TAF Time Alarm Flag 2 1 read-only 0 Time alarm has not occurred. #0 1 Time alarm has occurred. #1 TCE Time Counter Enable 4 1 read-write 0 Time counter is disabled. #0 1 Time counter is enabled. #1 TIF Time Invalid Flag 0 1 read-only 0 Time is valid. #0 1 Time is invalid and time counter is read as zero. #1 TOF Time Overflow Flag 1 1 read-only 0 Time overflow has not occurred. #0 1 Time overflow has occurred and time counter is read as zero. #1 TAR RTC Time Alarm Register 0x8 32 read-write n 0x0 0x0 TAR Time Alarm Register 0 32 read-write TCR RTC Time Compensation Register 0xC 32 read-write n 0x0 0x0 CIC Compensation Interval Counter 24 8 read-only CIR Compensation Interval Register 8 8 read-write TCR Time Compensation Register 0 8 read-write 0 Time Prescaler Register overflows every 32768 clock cycles. #0 1 Time Prescaler Register overflows every 32767 clock cycles. #1 10000000 Time Prescaler Register overflows every 32896 clock cycles. #10000000 1111111 Time Prescaler Register overflows every 32641 clock cycles. #1111111 11111111 Time Prescaler Register overflows every 32769 clock cycles. #11111111 TCV Time Compensation Value 16 8 read-only TPR RTC Time Prescaler Register 0x4 32 read-write n 0x0 0x0 TPR Time Prescaler Register 0 16 read-write TSR RTC Time Seconds Register 0x0 32 read-write n 0x0 0x0 TSR Time Seconds Register 0 32 read-write SCG System Clock Generator SCG 0x0 0x0 0x60C registers n SCG 43 CLKOUTCNFG SCG CLKOUT Configuration Register 0x20 32 read-write n 0x0 0x0 CLKOUTSEL SCG Clkout Select 24 4 read-write 0000 SCG SLOW Clock #0000 0001 System OSC #0001 0010 Slow IRC #0010 0011 Fast IRC #0011 0110 System PLL Reserved #0110 CSR Clock Status Register 0x10 32 read-only n 0x0 0x0 DIVCORE Core Clock Divide Ratio 16 4 read-only 0000 Divide-by-1 #0000 0001 Divide-by-2 #0001 0010 Divide-by-3 #0010 0011 Divide-by-4 #0011 0100 Divide-by-5 #0100 0101 Divide-by-6 #0101 0110 Divide-by-7 #0110 0111 Divide-by-8 #0111 1000 Divide-by-9 #1000 1001 Divide-by-10 #1001 1010 Divide-by-11 #1010 1011 Divide-by-12 #1011 1100 Divide-by-13 #1100 1101 Divide-by-14 #1101 1110 Divide-by-15 #1110 1111 Divide-by-16 #1111 DIVSLOW Slow Clock Divide Ratio 0 4 read-only 0000 Divide-by-1 #0000 0001 Divide-by-2 #0001 0010 Divide-by-3 #0010 0011 Divide-by-4 #0011 0100 Divide-by-5 #0100 0101 Divide-by-6 #0101 0110 Divide-by-7 #0110 0111 Divide-by-8 #0111 1000 Divide-by-9 #1000 1001 Divide-by-10 #1001 1010 Divide-by-11 #1010 1011 Divide-by-12 #1011 1100 Divide-by-13 #1100 1101 Divide-by-14 #1101 1110 Divide-by-15 #1110 1111 Divide-by-16 #1111 SCS System Clock Source 24 4 read-only 0001 System OSC #0001 0010 Slow IRC #0010 0011 Fast IRC #0011 0110 System PLL #0110 FIRCCFG Fast IRC Configuration Register 0x308 32 read-write n 0x0 0x0 RANGE Frequency Range 0 2 read-write 00 Fast IRC is trimmed to 48 MHz #00 01 Fast IRC is trimmed to 52 MHz #01 10 Fast IRC is trimmed to 56 MHz #10 11 Fast IRC is trimmed to 60 MHz #11 FIRCCSR Fast IRC Control Status Register 0x300 32 read-write n 0x0 0x0 FIRCEN Fast IRC Enable 0 1 read-write 0 Fast IRC is disabled #0 1 Fast IRC is enabled #1 FIRCERR Fast IRC Clock Error 26 1 read-write 0 Error not detected with the Fast IRC trimming. #0 1 Error detected with the Fast IRC trimming. #1 FIRCLPEN Fast IRC Low Power Enable 2 1 read-write 0 Fast IRC is disabled in VLP modes #0 1 Fast IRC is enabled in VLP modes #1 FIRCREGOFF Fast IRC Regulator Enable 3 1 read-write 0 Fast IRC Regulator is enabled. #0 1 Fast IRC Regulator is disabled. #1 FIRCSEL Fast IRC Selected 25 1 read-only 0 Fast IRC is not the system clock source #0 1 Fast IRC is the system clock source #1 FIRCSTEN Fast IRC Stop Enable 1 1 read-write 0 Fast IRC is disabled in Stop modes. When selected as the reference clock to the System PLL and if the System PLL is enabled in STOP mode, the Fast IRC will stay enabled even if FIRCSTEN=0. #0 1 Fast IRC is enabled in Stop modes #1 FIRCTREN Fast IRC Trim Enable 8 1 read-write 0 Disable trimming Fast IRC to an external clock source #0 1 Enable trimming Fast IRC to an external clock source #1 FIRCTRUP Fast IRC Trim Update 9 1 read-write 0 Disable Fast IRC trimming updates #0 1 Enable Fast IRC trimming updates #1 FIRCVLD Fast IRC Valid 24 1 read-only 0 Fast IRC is not enabled or clock is not valid #0 1 Fast IRC is enabled and output clock is valid #1 LK Lock Register 23 1 read-write 0 Control Status Register can be written. #0 1 Control Status Register cannot be written. #1 FIRCDIV Fast IRC Divide Register 0x304 32 read-write n 0x0 0x0 FIRCDIV1 Fast IRC Clock Divide 1 0 3 read-write 000 Output disabled #000 001 Divide by 1 #001 010 Divide by 2 #010 011 Divide by 4 #011 100 Divide by 8 #100 101 Divide by 16 #101 110 Divide by 32 #110 111 Divide by 64 #111 FIRCDIV2 Fast IRC Clock Divide 2 8 3 read-write 000 Output disabled #000 001 Divide by 1 #001 010 Divide by 2 #010 011 Divide by 4 #011 100 Divide by 8 #100 101 Divide by 16 #101 110 Divide by 32 #110 111 Divide by 64 #111 FIRCDIV3 Fast IRC Clock Divider 3 16 3 read-write 000 Clock disabled #000 001 Divide by 1 #001 010 Divide by 2 #010 011 Divide by 4 #011 100 Divide by 8 #100 101 Divide by 16 #101 110 Divide by 32 #110 111 Divide by 64 #111 FIRCSTAT Fast IRC Status Register 0x318 32 read-write n 0x0 0x0 TRIMCOAR Trim Coarse 8 6 read-write TRIMFINE Trim Fine Status 0 7 read-write FIRCTCFG Fast IRC Trim Configuration Register 0x30C 32 read-write n 0x0 0x0 TRIMDIV Fast IRC Trim Predivide 8 3 read-write 000 Divide by 1 #000 001 Divide by 128 #001 010 Divide by 256 #010 011 Divide by 512 #011 100 Divide by 1024 #100 101 Divide by 2048 #101 110 Reserved. Writing this value will result in Divide by 1. #110 111 Reserved. Writing this value will result in a Divide by 1. #111 TRIMSRC Trim Source 0 2 read-write 00 USB0 Start of Frame (1 kHz) #00 10 System OSC #10 HCCR HSRUN Clock Control Register 0x1C 32 read-write n 0x0 0x0 DIVCORE Core Clock Divide Ratio 16 4 read-write 0000 Divide-by-1 #0000 0001 Divide-by-2 #0001 0010 Divide-by-3 #0010 0011 Divide-by-4 #0011 0100 Divide-by-5 #0100 0101 Divide-by-6 #0101 0110 Divide-by-7 #0110 0111 Divide-by-8 #0111 1000 Divide-by-9 #1000 1001 Divide-by-10 #1001 1010 Divide-by-11 #1010 1011 Divide-by-12 #1011 1100 Divide-by-13 #1100 1101 Divide-by-14 #1101 1110 Divide-by-15 #1110 1111 Divide-by-16 #1111 DIVSLOW Slow Clock Divide Ratio 0 4 read-write 0000 Divide-by-1 #0000 0001 Divide-by-2 #0001 0010 Divide-by-3 #0010 0011 Divide-by-4 #0011 0100 Divide-by-5 #0100 0101 Divide-by-6 #0101 0110 Divide-by-7 #0110 0111 Divide-by-8 #0111 1000 Divide-by-9 #1000 1001 Divide-by-10 #1001 1010 Divide-by-11 #1010 1011 Divide-by-12 #1011 1100 Divide-by-13 #1100 1101 Divide-by-14 #1101 1110 Divide-by-15 #1110 1111 Divide-by-16 #1111 SCS System Clock Source 24 4 read-write 0001 System OSC #0001 0010 Slow IRC #0010 0011 Fast IRC #0011 0110 System PLL #0110 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 CLKPRES Clock Present 0 8 read-only DIVPRES Divider Present 27 5 read-only RCCR Run Clock Control Register 0x14 32 read-write n 0x0 0x0 DIVCORE Core Clock Divide Ratio 16 4 read-write 0000 Divide-by-1 #0000 0001 Divide-by-2 #0001 0010 Divide-by-3 #0010 0011 Divide-by-4 #0011 0100 Divide-by-5 #0100 0101 Divide-by-6 #0101 0110 Divide-by-7 #0110 0111 Divide-by-8 #0111 1000 Divide-by-9 #1000 1001 Divide-by-10 #1001 1010 Divide-by-11 #1010 1011 Divide-by-12 #1011 1100 Divide-by-13 #1100 1101 Divide-by-14 #1101 1110 Divide-by-15 #1110 1111 Divide-by-16 #1111 DIVSLOW Slow Clock Divide Ratio 0 4 read-write 0000 Divide-by-1 #0000 0001 Divide-by-2 #0001 0010 Divide-by-3 #0010 0011 Divide-by-4 #0011 0100 Divide-by-5 #0100 0101 Divide-by-6 #0101 0110 Divide-by-7 #0110 0111 Divide-by-8 #0111 1000 Divide-by-9 #1000 1001 Divide-by-10 #1001 1010 Divide-by-11 #1010 1011 Divide-by-12 #1011 1100 Divide-by-13 #1100 1101 Divide-by-14 #1101 1110 Divide-by-15 #1110 1111 Divide-by-16 #1111 SCS System Clock Source 24 4 read-write 0001 System OSC #0001 0010 Slow IRC #0010 0011 Fast IRC #0011 0110 System PLL #0110 SIRCCFG Slow IRC Configuration Register 0x208 32 read-write n 0x0 0x0 RANGE Frequency Range 0 1 read-write 0 Slow IRC low range clock (2 MHz) #0 1 Slow IRC high range clock (8 MHz ) #1 SIRCCSR Slow IRC Control Status Register 0x200 32 read-write n 0x0 0x0 LK Lock Register 23 1 read-write 0 Control Status Register can be written. #0 1 Control Status Register cannot be written. #1 SIRCEN Slow IRC Enable 0 1 read-write 0 Slow IRC is disabled #0 1 Slow IRC is enabled #1 SIRCLPEN Slow IRC Low Power Enable 2 1 read-write 0 Slow IRC is disabled in VLP modes #0 1 Slow IRC is enabled in VLP modes #1 SIRCSEL Slow IRC Selected 25 1 read-only 0 Slow IRC is not the system clock source #0 1 Slow IRC is the system clock source #1 SIRCSTEN Slow IRC Stop Enable 1 1 read-write 0 Slow IRC is disabled in Stop modes #0 1 Slow IRC is enabled in Stop modes #1 SIRCVLD Slow IRC Valid 24 1 read-only 0 Slow IRC is not enabled or clock is not valid #0 1 Slow IRC is enabled and output clock is valid #1 SIRCDIV Slow IRC Divide Register 0x204 32 read-write n 0x0 0x0 SIRCDIV1 Slow IRC Clock Divide 1 0 3 read-write 000 Output disabled #000 001 Divide by 1 #001 010 Divide by 2 #010 011 Divide by 4 #011 100 Divide by 8 #100 101 Divide by 16 #101 110 Divide by 32 #110 111 Divide by 64 #111 SIRCDIV2 Slow IRC Clock Divide 2 8 3 read-write 000 Output disabled #000 001 Divide by 1 #001 010 Divide by 2 #010 011 Divide by 4 #011 100 Divide by 8 #100 101 Divide by 16 #101 110 Divide by 32 #110 111 Divide by 64 #111 SIRCDIV3 Slow IRC Clock Divider 3 16 3 read-write 000 Output disabled #000 001 Divide by 1 #001 010 Divide by 2 #010 011 Divide by 4 #011 100 Divide by 8 #100 101 Divide by 16 #101 110 Divide by 32 #110 111 Divide by 64 #111 SOSCCFG System Oscillator Configuration Register 0x108 32 read-write n 0x0 0x0 EREFS External Reference Select 2 1 read-write 0 External reference clock selected #0 1 Internal crystal oscillator of OSC requested. In VLLS0, the internal oscillator of OSC is disabled even if SOSCEN=1 and SOSCSTEN=1. #1 HGO High Gain Oscillator Select 3 1 read-write 0 Configure crystal oscillaor for low-power operation #0 1 Configure crystal oscillator for high-gain operation #1 RANGE System OSC Range Select 4 2 read-write 01 Low frequency range selected for the crystal oscillator of 32 kHz to 40 kHz. #01 10 Medium frequency range selected for the crytstal oscillator of 1 Mhz to 8 Mhz. #10 11 High frequency range selected for the crystal oscillator of 8 Mhz to 32 Mhz. #11 SC16P Oscillator 16 pF Capacitor Load 8 1 read-write SC2P Oscillator 2 pF Capacitor Load 11 1 read-write SC4P Oscillator 4 pF Capacitor Load 10 1 read-write SC8P Oscillator 8 pF Capacitor Load Configure 9 1 read-write SOSCCSR System OSC Control Status Register 0x100 32 read-write n 0x0 0x0 LK Lock Register 23 1 read-write 0 This Control Status Register can be written. #0 1 This Control Status Register cannot be written. #1 SOSCCM System OSC Clock Monitor 16 1 read-write 0 System OSC Clock Monitor is disabled #0 1 System OSC Clock Monitor is enabled #1 SOSCCMRE System OSC Clock Monitor Reset Enable 17 1 read-write 0 Clock Monitor generates interrupt when error detected #0 1 Clock Monitor generates reset when error detected #1 SOSCEN System OSC Enable 0 1 read-write 0 System OSC is disabled #0 1 System OSC is enabled #1 SOSCERCLKEN System OSC 3V ERCLK Enable 3 1 read-write 0 System OSC 3V ERCLK output clock is disabled. #0 1 System OSC 3V ERCLK output clock is enabled when SYSOSC is enabled. #1 SOSCERR System OSC Clock Error 26 1 read-write 0 System OSC Clock Monitor is disabled or has not detected an error #0 1 System OSC Clock Monitor is enabled and detected an error #1 SOSCLPEN System OSC Low Power Enable 2 1 read-write 0 System OSC is disabled in VLP modes #0 1 System OSC is enabled in VLP modes #1 SOSCSEL System OSC Selected 25 1 read-only 0 System OSC is not the system clock source #0 1 System OSC is the system clock source #1 SOSCSTEN System OSC Stop Enable 1 1 read-write 0 System OSC is disabled in Stop modes #0 1 System OSC is enabled in Stop modes if SOSCEN=1. In VLLS0, system oscillator is disabled even if SOSCSTEN=1 and SOSCEN=1. #1 SOSCVLD System OSC Valid 24 1 read-only 0 System OSC is not enabled or clock is not valid #0 1 System OSC is enabled and output clock is valid #1 SOSCDIV System OSC Divide Register 0x104 32 read-write n 0x0 0x0 SOSCDIV1 System OSC Clock Divide 1 0 3 read-write 000 Output disabled #000 001 Divide by 1 #001 010 Divide by 2 #010 011 Divide by 4 #011 100 Divide by 8 #100 101 Divide by 16 #101 110 Divide by 32 #110 111 Divide by 64 #111 SOSCDIV2 System OSC Clock Divide 2 8 3 read-write 000 Output disabled #000 001 Divide by 1 #001 010 Divide by 2 #010 011 Divide by 4 #011 100 Divide by 8 #100 101 Divide by 16 #101 110 Divide by 32 #110 111 Divide by 64 #111 SOSCDIV3 System OSC Clock Divide 3 16 3 read-write 000 Output disabled #000 001 Divide by 1 #001 010 Divide by 2 #010 011 Divide by 4 #011 100 Divide by 8 #100 101 Divide by 16 #101 110 Divide by 32 #110 111 Divide by 64 #111 SPLLCFG System PLL Configuration Register 0x608 32 read-write n 0x0 0x0 MULT System PLL Multiplier 16 5 read-write PREDIV PLL Reference Clock Divider 8 3 read-write SOURCE Clock Source 0 1 read-write 0 System OSC #0 1 Fast IRC #1 SPLLCSR System PLL Control Status Register 0x600 32 read-write n 0x0 0x0 LK Lock Register 23 1 read-write 0 Control Status Register can be written. #0 1 Control Status Register cannot be written. #1 SPLLCM System PLL Clock Monitor 16 1 read-write 0 System PLL Clock Monitor is disabled #0 1 System PLL Clock Monitor is enabled #1 SPLLCMRE System PLL Clock Monitor Reset Enable 17 1 read-write 0 Clock Monitor generates interrupt when error detected #0 1 Clock Monitor generates reset when error detected #1 SPLLEN System PLL Enable 0 1 read-write 0 System PLL is disabled #0 1 System PLL is enabled #1 SPLLERR System PLL Clock Error 26 1 read-write 0 System PLL Clock Monitor is disabled or has not detected an error #0 1 System PLL Clock Monitor is enabled and detected an error. System PLL Clock Error flag will not set when System OSC is selected as its source and SOSCERR has set. #1 SPLLSEL System PLL Selected 25 1 read-only 0 System PLL is not the system clock source #0 1 System PLL is the system clock source #1 SPLLSTEN System PLL Stop Enable 1 1 read-write 0 System PLL is disabled in Stop modes #0 1 System PLL is enabled in Stop modes #1 SPLLVLD System PLL Valid 24 1 read-only 0 System PLL is not enabled or clock is not valid #0 1 System PLL is enabled and output clock is valid #1 SPLLDIV System PLL Divide Register 0x604 32 read-write n 0x0 0x0 SPLLDIV1 System PLL Clock Divide 1 0 3 read-write 000 Clock disabled #000 001 Divide by 1 #001 010 Divide by 2 #010 011 Divide by 4 #011 100 Divide by 8 #100 101 Divide by 16 #101 110 Divide by 32 #110 111 Divide by 64 #111 SPLLDIV2 System PLL Clock Divide 2 8 3 read-write 000 Clock disabled #000 001 Divide by 1 #001 010 Divide by 2 #010 011 Divide by 4 #011 100 Divide by 8 #100 101 Divide by 16 #101 110 Divide by 32 #110 111 Divide by 64 #111 SPLLDIV3 System PLL Clock Divide 3 16 3 read-write 000 Clock disabled #000 001 Divide by 1 #001 010 Divide by 2 #010 011 Divide by 4 #011 100 Divide by 8 #100 101 Divide by 16 #101 110 Divide by 32 #110 111 Divide by 64 #111 VCCR VLPR Clock Control Register 0x18 32 read-write n 0x0 0x0 DIVCORE Core Clock Divide Ratio 16 4 read-write 0000 Divide-by-1 #0000 0001 Divide-by-2 #0001 0010 Divide-by-3 #0010 0011 Divide-by-4 #0011 0100 Divide-by-5 #0100 0101 Divide-by-6 #0101 0110 Divide-by-7 #0110 0111 Divide-by-8 #0111 1000 Divide-by-9 #1000 1001 Divide-by-10 #1001 1010 Divide-by-11 #1010 1011 Divide-by-12 #1011 1100 Divide-by-13 #1100 1101 Divide-by-14 #1101 1110 Divide-by-15 #1110 1111 Divide-by-16 #1111 DIVSLOW Slow Clock Divide Ratio 0 4 read-write 0000 Divide-by-1 #0000 0001 Divide-by-2 #0001 0010 Divide-by-3 #0010 0011 Divide-by-4 #0011 0100 Divide-by-5 #0100 0101 Divide-by-6 #0101 0110 Divide-by-7 #0110 0111 Divide-by-8 #0111 1000 Divide-by-9 #1000 1001 Divide-by-10 #1001 1010 Divide-by-11 #1010 1011 Divide-by-12 #1011 1100 Divide-by-13 #1100 1101 Divide-by-14 #1101 1110 Divide-by-15 #1110 1111 Divide-by-16 #1111 SCS System Clock Source 24 4 read-write 0001 System OSC #0001 0010 Slow IRC #0010 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 VERSION SCG Version Number 0 32 read-only SEMA420 SEMA42 SEMA42 0x0 0x0 0x44 registers n GATE0 Gate Register 0x6 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE1 Gate Register 0x3 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE10 Gate Register 0x2D 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE11 Gate Register 0x24 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE12 Gate Register 0x78 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE13 Gate Register 0x69 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE14 Gate Register 0x5B 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE15 Gate Register 0x4E 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE2 Gate Register 0x1 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE3 Gate Register 0x0 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE4 Gate Register 0x1C 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE5 Gate Register 0x15 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE6 Gate Register 0xF 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE7 Gate Register 0xA 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE8 Gate Register 0x42 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE9 Gate Register 0x37 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 RSTGT_R Reset Gate Read SEMA420 0x42 16 read-only n 0x0 0x0 ROZ This field always returns the value 0 when read. 14 2 read-only RSTGMS Reset Gate Bus Master 8 4 read-only RSTGSM Reset Gate Finite State Machine 12 2 read-only 00 Idle, waiting for the first data pattern write. #00 01 Waiting for the second data pattern write. #01 10 The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed, this machine returns to the idle (waiting for first data pattern write) state. The "01" state persists for only one clock cycle. Software cannot observe this state. #10 11 This state encoding is never used and therefore reserved. #11 RSTGTN Reset Gate Number 0 8 read-only RSTGT_W Reset Gate Write SEMA420 0x42 16 write-only n 0x0 0x0 RSTGDP Reset Gate Data Pattern 8 8 write-only RSTGTN Reset Gate Number 0 8 write-only SEMA421 SEMA42 SEMA42 0x0 0x0 0x44 registers n GATE0 Gate Register 0x6 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE1 Gate Register 0x3 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE10 Gate Register 0x2D 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE11 Gate Register 0x24 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE12 Gate Register 0x78 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE13 Gate Register 0x69 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE14 Gate Register 0x5B 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE15 Gate Register 0x4E 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE2 Gate Register 0x1 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE3 Gate Register 0x0 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE4 Gate Register 0x1C 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE5 Gate Register 0x15 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE6 Gate Register 0xF 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE7 Gate Register 0xA 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE8 Gate Register 0x42 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 GATE9 Gate Register 0x37 8 read-write n 0x0 0x0 GTFSM Gate Finite State Machine. 0 4 read-write 0000 The gate is unlocked (free). #0000 0001 The gate has been locked by processor 0. #0001 0010 The gate has been locked by processor 1. #0010 0011 The gate has been locked by processor 2. #0011 0100 The gate has been locked by processor 3. #0100 0101 The gate has been locked by processor 4. #0101 0110 The gate has been locked by processor 5. #0110 0111 The gate has been locked by processor 6. #0111 1000 The gate has been locked by processor 7. #1000 1001 The gate has been locked by processor 8. #1001 1010 The gate has been locked by processor 9. #1010 1011 The gate has been locked by processor 10. #1011 1100 The gate has been locked by processor 11. #1100 1101 The gate has been locked by processor 12. #1101 1110 The gate has been locked by processor 13. #1110 1111 The gate has been locked by processor 14. #1111 RSTGT_R Reset Gate Read SEMA421 0x42 16 read-only n 0x0 0x0 ROZ This field always returns the value 0 when read. 14 2 read-only RSTGMS Reset Gate Bus Master 8 4 read-only RSTGSM Reset Gate Finite State Machine 12 2 read-only 00 Idle, waiting for the first data pattern write. #00 01 Waiting for the second data pattern write. #01 10 The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed, this machine returns to the idle (waiting for first data pattern write) state. The "01" state persists for only one clock cycle. Software cannot observe this state. #10 11 This state encoding is never used and therefore reserved. #11 RSTGTN Reset Gate Number 0 8 read-only RSTGT_W Reset Gate Write SEMA421 0x42 16 write-only n 0x0 0x0 RSTGDP Reset Gate Data Pattern 8 8 write-only RSTGTN Reset Gate Number 0 8 write-only SIM System Integration Module SIM 0x0 0x0 0x10F0 registers n FCFG1 Flash Configuration Register 1 0x104C 32 read-write n 0x0 0x0 FLASHDIS Flash Disable 0 1 read-write 0 Flash is enabled. #0 1 Flash is disabled. #1 FLASHDOZE Flash Doze 1 1 read-write 0 Flash remains enabled during Doze mode. #0 1 Flash is disabled for the duration of Doze mode. #1 PFSIZE Program Flash Size 24 4 read-only 0101 64 KB of program flash memory, 2 KB protection region #0101 0111 128 KB of program flash memory, 4 KB protection region #0111 1001 256 KB of program flash memory, 8 KB protection region #1001 1011 512 KB of program flash memory, 16 KB protection region #1011 FCFG2 Flash Configuration Register 2 0x1050 32 read-only n 0x0 0x0 MAXADDR0 Max Address lock 24 7 read-only PCSR Peripheral Clock Status Register 0x10EC 32 read-only n 0x0 0x0 CS1 Clock Source 1 1 1 read-only 0 Clock not ready. #0 1 Clock ready. #1 CS2 Clock Source 2 2 1 read-only 0 Clock not ready. #0 1 Clock ready. #1 CS3 Clock Source 3 3 1 read-only 0 Clock not ready. #0 1 Clock ready. #1 CS4 Clock Source 4 4 1 read-only 0 Clock not ready. #0 1 Clock ready. #1 CS5 Clock Source 5 5 1 read-only 0 Clock not ready. #0 1 Clock ready. #1 CS6 Clock Source 6 6 1 read-only 0 Clock not ready. #0 1 Clock ready. #1 CS7 Clock Source 7 7 1 read-only 0 Clock not ready. #0 1 Clock ready. #1 SDID System Device Identification Register 0x1024 32 read-only n 0x0 0x0 DIEID Device Die Number 7 5 read-only FAMID Kinetis family ID 28 4 read-only 0010 KL2x Family (USB) #0010 KEYATT Core configuration of the device. 4 3 read-only 000 Cortex CM0+ Core #000 001 Cortex CM0+ Core with additional Core (Core0 and Core1) #001 PINID Pin count identification 0 4 read-only 0000 16-pin #0000 0001 24-pin #0001 0010 32-pin #0010 0011 36-pin #0011 0100 48-pin #0100 0101 64-pin #0101 0110 80-pin #0110 1000 100-pin #1000 1001 121-pin #1001 1011 Custom pin-out(WLCSP) #1011 REVID Device Revision Number 12 4 read-only SERIESID Kinetis Series ID 20 4 read-only 0001 KL family #0001 SRAMSIZE System SRAM Size 16 4 read-only 1000 96 KB #1000 1001 128 KB #1001 SUBFAMID Kinetis Sub-Family ID 24 4 read-only 0010 KLx2 Subfamily #0010 0011 KLx3 Subfamily #0011 0100 KLx4 Subfamily #0100 0101 KLx5 Subfamily #0101 0110 KLx6 Subfamily #0110 0111 KLx7 Subfamily #0111 1000 KLx8 Subfamily #1000 1001 KLx9 Subfamily #1001 SOPT1 System Options Register 1 0x0 32 read-write n 0x0 0x0 USBREGEN USB voltage regulator enable 31 1 read-write 0 USB voltage regulator is disabled. #0 1 USB voltage regulator is enabled. #1 USBSSTBY USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes. 30 1 read-write 0 USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS modes. #0 1 USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes. #1 USBVSTBY USB voltage regulator in standby mode during VLPR and VLPW modes 29 1 read-write 0 USB voltage regulator not in standby during VLPR and VLPW modes. #0 1 USB voltage regulator in standby during VLPR and VLPW modes. #1 SOPT1CFG SOPT1 Configuration Register 0x4 32 read-write n 0x0 0x0 URWE USB voltage regulator enable write enable 24 1 read-write 0 SOPT1 USBREGEN cannot be written. #0 1 SOPT1 USBREGEN can be written. #1 USSWE USB voltage regulator stop standby write enable 26 1 read-write 0 SOPT1 USBSSTB cannot be written. #0 1 SOPT1 USBSSTB can be written. #1 UVSWE USB voltage regulator VLP standby write enable 25 1 read-write 0 SOPT1 USBVSTB cannot be written. #0 1 SOPT1 USBVSTB can be written. #1 UIDL Unique Identification Register Low 0x1060 32 read-only n 0x0 0x0 UID Unique Identification 0 32 read-only UIDMH Unique Identification Register Mid-High 0x1058 32 read-only n 0x0 0x0 UID Unique Identification 0 16 read-only UIDML Unique Identification Register Mid Low 0x105C 32 read-only n 0x0 0x0 UID Unique Identification 0 32 read-only SMC System Mode Controller SMC 0x0 0x0 0x18 registers n PARAM SMC Parameter Register 0x4 32 read-only n 0x0 0x0 EHSRUN Enable HSRUN 0 1 read-only ELLS Enable LLS (if this mode exists on the SOC) 3 1 read-only ELLS2 Enable LLS2 (if this mode exists on the SOC) 5 1 read-only EVLLS0 Enable VLLS0 (if this mode exists on the SOC) 6 1 read-only PMCTRL Power Mode Control register 0xC 32 read-write n 0x0 0x0 RUNM Run Mode Control 5 2 read-write 00 Normal Run mode (RUN) #00 10 Very-Low-Power Run mode (VLPR) #10 11 High Speed Run mode (HSRUN) #11 STOPA Stop Aborted 3 1 read-only 0 The previous stop mode entry was successsful. #0 1 The previous stop mode entry was aborted. #1 STOPM Stop Mode Control 0 3 read-write 000 Normal Stop (STOP) #000 010 Very-Low-Power Stop (VLPS) #010 011 Low-Leakage Stop (LLSx) #011 100 Very-Low-Leakage Stop (VLLSx) #100 110 Reseved #110 PMPROT Power Mode Protection register 0x8 32 read-write n 0x0 0x0 AHSRUN Allow High Speed Run mode 7 1 read-write 0 HSRUN is not allowed #0 1 HSRUN is allowed #1 ALLS Allow Low-Leakage Stop Mode 3 1 read-write 0 Any LLSx mode is not allowed #0 1 Any LLSx mode is allowed #1 AVLLS Allow Very-Low-Leakage Stop Mode 1 1 read-write 0 Any VLLSx mode is not allowed #0 1 Any VLLSx mode is allowed #1 AVLP Allow Very-Low-Power Modes 5 1 read-write 0 VLPR, VLPW, and VLPS are not allowed. #0 1 VLPR, VLPW, and VLPS are allowed. #1 PMSTAT Power Mode Status register 0x14 32 read-only n 0x0 0x0 PMSTAT Power Mode Status 0 8 read-only STOPCTRL Stop Control Register 0x10 32 read-write n 0x0 0x0 LLSM LLS or VLLS Mode Control 0 3 read-write 000 VLLS0 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx #000 001 VLLS1 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx #001 010 VLLS2 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx #010 011 VLLS3 if PMCTRL[STOPM]=VLLSx, LLS3 if PMCTRL[STOPM]=LLSx #011 LPOPO LPO Power Option 3 1 read-write 0 LPO clock is enabled in LLS/VLLSx #0 1 LPO clock is disabled in LLS/VLLSx #1 PORPO POR Power Option 5 1 read-write 0 POR detect circuit is enabled in VLLS0 #0 1 POR detect circuit is disabled in VLLS0 #1 PSTOPO Partial Stop Option 6 2 read-write 00 STOP - Normal Stop mode #00 01 PSTOP1 - Partial Stop with both system and bus clocks disabled #01 10 PSTOP2 - Partial Stop with system clock disabled and bus clock enabled #10 VERID SMC Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Specification Number 0 16 read-only 0 Standard features implemented #0 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only TPM0 Timer/PWM Module TPM 0x0 0x0 0x88 registers n TPM0 6 C0SC Channel (n) Status and Control 0x40 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C0V Channel (n) Value 0x48 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C1SC Channel (n) Status and Control 0x68 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C1V Channel (n) Value 0x74 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C2SC Channel (n) Status and Control 0x98 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C2V Channel (n) Value 0xA8 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C3SC Channel (n) Status and Control 0xD0 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C3V Channel (n) Value 0xE4 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C4SC Channel (n) Status and Control 0x110 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C4V Channel (n) Value 0x128 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C5SC Channel (n) Status and Control 0x158 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C5V Channel (n) Value 0x174 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CNT Counter 0x14 32 read-write n 0x0 0x0 COUNT Counter value 0 16 read-write COMBINE Combine Channel Register 0x64 32 read-write n 0x0 0x0 COMBINE0 Combine Channels 0 and 1 0 1 read-write 0 Channels 0 and 1 are independent. #0 1 Channels 0 and 1 are combined. #1 COMBINE1 Combine Channels 2 and 3 8 1 read-write 0 Channels 2 and 3 are independent. #0 1 Channels 2 and 3 are combined. #1 COMBINE2 Combine Channels 4 and 5 16 1 read-write 0 Channels 4 and 5 are independent. #0 1 Channels 4 and 5 are combined. #1 COMSWAP0 Combine Channel 0 and 1 Swap 1 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 COMSWAP1 Combine Channels 2 and 3 Swap 9 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 COMSWAP2 Combine Channels 4 and 5 Swap 17 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 CONF Configuration 0x84 32 read-write n 0x0 0x0 CPOT Counter Pause On Trigger 19 1 read-write CROT Counter Reload On Trigger 18 1 read-write 0 Counter is not reloaded due to a rising edge on the selected input trigger #0 1 Counter is reloaded when a rising edge is detected on the selected input trigger #1 CSOO Counter Stop On Overflow 17 1 read-write 0 TPM counter continues incrementing or decrementing after overflow #0 1 TPM counter stops incrementing or decrementing after overflow. #1 CSOT Counter Start on Trigger 16 1 read-write 0 TPM counter starts to increment immediately, once it is enabled. #0 1 TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow. #1 DBGMODE Debug Mode 6 2 read-write 00 TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored. #00 11 TPM counter continues in debug mode. #11 DOZEEN Doze Enable 5 1 read-write 0 Internal TPM counter continues in Doze mode. #0 1 Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored. #1 GTBEEN Global time base enable 9 1 read-write 0 All channels use the internally generated TPM counter as their timebase #0 1 All channels use an externally generated global timebase as their timebase #1 GTBSYNC Global Time Base Synchronization 8 1 read-write 0 Global timebase synchronization disabled. #0 1 Global timebase synchronization enabled. #1 TRGPOL Trigger Polarity 22 1 read-write 0 Trigger is active high. #0 1 Trigger is active low. #1 TRGSEL Trigger Select 24 2 read-write TRGSRC Trigger Source 23 1 read-write 0 Trigger source selected by TRGSEL is external. #0 1 Trigger source selected by TRGSEL is internal (channel pin input capture). #1 FILTER Filter Control 0x78 32 read-write n 0x0 0x0 CH0FVAL Channel 0 Filter Value 0 4 read-write CH1FVAL Channel 1 Filter Value 4 4 read-write CH2FVAL Channel 2 Filter Value 8 4 read-write CH3FVAL Channel 3 Filter Value 12 4 read-write CH4FVAL Channel 4 Filter Value 16 4 read-write CH5FVAL Channel 5 Filter Value 20 4 read-write GLOBAL TPM Global Register 0x8 32 read-write n 0x0 0x0 RST Software Reset 1 1 read-write 0 Module is not reset. #0 1 Module is reset. #1 MOD Modulo 0x18 32 read-write n 0x0 0x0 MOD Modulo value 0 16 read-write PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 CHAN Channel Count 0 8 read-only TRIG Trigger Count 8 8 read-only WIDTH Counter Width 16 8 read-only POL Channel Polarity 0x70 32 read-write n 0x0 0x0 POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 QDCTRL Quadrature Decoder Control and Status 0x80 32 read-write n 0x0 0x0 QUADEN Enables the quadrature decoder mode 0 1 read-write 0 Quadrature decoder mode is disabled. #0 1 Quadrature decoder mode is enabled. #1 QUADIR Counter Direction in Quadrature Decode Mode 2 1 read-only 0 Counter direction is decreasing (counter decrement). #0 1 Counter direction is increasing (counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase encoding mode. #0 1 Count and direction encoding mode. #1 TOFDIR Indicates if the TOF bit was set on the top or the bottom of counting. 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero). #1 SC Status and Control 0x10 32 read-write n 0x0 0x0 CMOD Clock Mode Selection 3 2 read-write 00 TPM counter is disabled #00 01 TPM counter increments on every TPM counter clock #01 10 TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock #10 11 TPM counter increments on rising edge of the selected external input trigger. #11 CPWMS Center-Aligned PWM Select 5 1 read-write 0 TPM counter operates in up counting mode. #0 1 TPM counter operates in up-down counting mode. #1 DMA DMA Enable 8 1 read-write 0 Disables DMA transfers. #0 1 Enables DMA transfers. #1 PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 TOF Timer Overflow Flag 7 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling or DMA request. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 STATUS Capture and Compare Status 0x1C 32 read-write n 0x0 0x0 CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 TOF Timer Overflow Flag 8 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 TRIG Channel Trigger 0x6C 32 read-write n 0x0 0x0 TRIG0 Channel 0 Trigger 0 1 read-write 0 No effect. #0 1 The input trigger is used for input capture and modulates output (for output compare and PWM). #1 TRIG1 Channel 1 Trigger 1 1 read-write 0 No effect. #0 1 The input trigger is used for input capture and modulates output (for output compare and PWM). #1 TRIG2 Channel 2 Trigger 2 1 read-write 0 No effect. #0 1 The input trigger is used for input capture and modulates output (for output compare and PWM). #1 TRIG3 Channel 3 Trigger 3 1 read-write 0 No effect. #0 1 The input trigger is used for input capture and modulates output (for output compare and PWM). #1 TRIG4 Channel 4 Trigger 4 1 read-write 0 No effect. #0 1 The input trigger is used for input capture and modulates output (for output compare and PWM). #1 TRIG5 Channel 5 Trigger 5 1 read-write 0 No effect. #0 1 The input trigger is used for input capture and modulates output (for output compare and PWM). #1 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Identification Number 0 16 read-only 1 Standard feature set. #1 11 Standard feature set with Filter and Combine registers implemented. #11 111 Standard feature set with Filter, Combine and Quadrature registers implemented. #111 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only TPM1 Timer/PWM Module TPM 0x0 0x0 0x88 registers n TPM1 7 C0SC Channel (n) Status and Control 0x40 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C0V Channel (n) Value 0x48 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C1SC Channel (n) Status and Control 0x68 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C1V Channel (n) Value 0x74 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CNT Counter 0x14 32 read-write n 0x0 0x0 COUNT Counter value 0 16 read-write COMBINE Combine Channel Register 0x64 32 read-write n 0x0 0x0 COMBINE0 Combine Channels 0 and 1 0 1 read-write 0 Channels 0 and 1 are independent. #0 1 Channels 0 and 1 are combined. #1 COMBINE1 Combine Channels 2 and 3 8 1 read-write 0 Channels 2 and 3 are independent. #0 1 Channels 2 and 3 are combined. #1 COMBINE2 Combine Channels 4 and 5 16 1 read-write 0 Channels 4 and 5 are independent. #0 1 Channels 4 and 5 are combined. #1 COMSWAP0 Combine Channel 0 and 1 Swap 1 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 COMSWAP1 Combine Channels 2 and 3 Swap 9 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 COMSWAP2 Combine Channels 4 and 5 Swap 17 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 CONF Configuration 0x84 32 read-write n 0x0 0x0 CPOT Counter Pause On Trigger 19 1 read-write CROT Counter Reload On Trigger 18 1 read-write 0 Counter is not reloaded due to a rising edge on the selected input trigger #0 1 Counter is reloaded when a rising edge is detected on the selected input trigger #1 CSOO Counter Stop On Overflow 17 1 read-write 0 TPM counter continues incrementing or decrementing after overflow #0 1 TPM counter stops incrementing or decrementing after overflow. #1 CSOT Counter Start on Trigger 16 1 read-write 0 TPM counter starts to increment immediately, once it is enabled. #0 1 TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow. #1 DBGMODE Debug Mode 6 2 read-write 00 TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored. #00 11 TPM counter continues in debug mode. #11 DOZEEN Doze Enable 5 1 read-write 0 Internal TPM counter continues in Doze mode. #0 1 Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored. #1 GTBEEN Global time base enable 9 1 read-write 0 All channels use the internally generated TPM counter as their timebase #0 1 All channels use an externally generated global timebase as their timebase #1 GTBSYNC Global Time Base Synchronization 8 1 read-write 0 Global timebase synchronization disabled. #0 1 Global timebase synchronization enabled. #1 TRGPOL Trigger Polarity 22 1 read-write 0 Trigger is active high. #0 1 Trigger is active low. #1 TRGSEL Trigger Select 24 2 read-write TRGSRC Trigger Source 23 1 read-write 0 Trigger source selected by TRGSEL is external. #0 1 Trigger source selected by TRGSEL is internal (channel pin input capture). #1 FILTER Filter Control 0x78 32 read-write n 0x0 0x0 CH0FVAL Channel 0 Filter Value 0 4 read-write CH1FVAL Channel 1 Filter Value 4 4 read-write CH2FVAL Channel 2 Filter Value 8 4 read-write CH3FVAL Channel 3 Filter Value 12 4 read-write CH4FVAL Channel 4 Filter Value 16 4 read-write CH5FVAL Channel 5 Filter Value 20 4 read-write GLOBAL TPM Global Register 0x8 32 read-write n 0x0 0x0 RST Software Reset 1 1 read-write 0 Module is not reset. #0 1 Module is reset. #1 MOD Modulo 0x18 32 read-write n 0x0 0x0 MOD Modulo value 0 16 read-write PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 CHAN Channel Count 0 8 read-only TRIG Trigger Count 8 8 read-only WIDTH Counter Width 16 8 read-only POL Channel Polarity 0x70 32 read-write n 0x0 0x0 POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 QDCTRL Quadrature Decoder Control and Status 0x80 32 read-write n 0x0 0x0 QUADEN Enables the quadrature decoder mode 0 1 read-write 0 Quadrature decoder mode is disabled. #0 1 Quadrature decoder mode is enabled. #1 QUADIR Counter Direction in Quadrature Decode Mode 2 1 read-only 0 Counter direction is decreasing (counter decrement). #0 1 Counter direction is increasing (counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase encoding mode. #0 1 Count and direction encoding mode. #1 TOFDIR Indicates if the TOF bit was set on the top or the bottom of counting. 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero). #1 SC Status and Control 0x10 32 read-write n 0x0 0x0 CMOD Clock Mode Selection 3 2 read-write 00 TPM counter is disabled #00 01 TPM counter increments on every TPM counter clock #01 10 TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock #10 11 TPM counter increments on rising edge of the selected external input trigger. #11 CPWMS Center-Aligned PWM Select 5 1 read-write 0 TPM counter operates in up counting mode. #0 1 TPM counter operates in up-down counting mode. #1 DMA DMA Enable 8 1 read-write 0 Disables DMA transfers. #0 1 Enables DMA transfers. #1 PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 TOF Timer Overflow Flag 7 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling or DMA request. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 STATUS Capture and Compare Status 0x1C 32 read-write n 0x0 0x0 CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 TOF Timer Overflow Flag 8 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 TRIG Channel Trigger 0x6C 32 read-write n 0x0 0x0 TRIG0 Channel 0 Trigger 0 1 read-write 0 No effect. #0 1 The input trigger is used for input capture and modulates output (for output compare and PWM). #1 TRIG1 Channel 1 Trigger 1 1 read-write 0 No effect. #0 1 The input trigger is used for input capture and modulates output (for output compare and PWM). #1 TRIG2 Channel 2 Trigger 2 1 read-write 0 No effect. #0 1 The input trigger is used for input capture and modulates output (for output compare and PWM). #1 TRIG3 Channel 3 Trigger 3 1 read-write 0 No effect. #0 1 The input trigger is used for input capture and modulates output (for output compare and PWM). #1 TRIG4 Channel 4 Trigger 4 1 read-write 0 No effect. #0 1 The input trigger is used for input capture and modulates output (for output compare and PWM). #1 TRIG5 Channel 5 Trigger 5 1 read-write 0 No effect. #0 1 The input trigger is used for input capture and modulates output (for output compare and PWM). #1 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Identification Number 0 16 read-only 1 Standard feature set. #1 11 Standard feature set with Filter and Combine registers implemented. #11 111 Standard feature set with Filter, Combine and Quadrature registers implemented. #111 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only TPM2 Timer/PWM Module TPM 0x0 0x0 0x88 registers n TPM2 8 C0SC Channel (n) Status and Control 0x40 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C0V Channel (n) Value 0x48 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write C1SC Channel (n) Status and Control 0x68 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write C1V Channel (n) Value 0x74 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CNT Counter 0x14 32 read-write n 0x0 0x0 COUNT Counter value 0 16 read-write COMBINE Combine Channel Register 0x64 32 read-write n 0x0 0x0 COMBINE0 Combine Channels 0 and 1 0 1 read-write 0 Channels 0 and 1 are independent. #0 1 Channels 0 and 1 are combined. #1 COMBINE1 Combine Channels 2 and 3 8 1 read-write 0 Channels 2 and 3 are independent. #0 1 Channels 2 and 3 are combined. #1 COMBINE2 Combine Channels 4 and 5 16 1 read-write 0 Channels 4 and 5 are independent. #0 1 Channels 4 and 5 are combined. #1 COMSWAP0 Combine Channel 0 and 1 Swap 1 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 COMSWAP1 Combine Channels 2 and 3 Swap 9 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 COMSWAP2 Combine Channels 4 and 5 Swap 17 1 read-write 0 Even channel is used for input capture and 1st compare. #0 1 Odd channel is used for input capture and 1st compare. #1 CONF Configuration 0x84 32 read-write n 0x0 0x0 CPOT Counter Pause On Trigger 19 1 read-write CROT Counter Reload On Trigger 18 1 read-write 0 Counter is not reloaded due to a rising edge on the selected input trigger #0 1 Counter is reloaded when a rising edge is detected on the selected input trigger #1 CSOO Counter Stop On Overflow 17 1 read-write 0 TPM counter continues incrementing or decrementing after overflow #0 1 TPM counter stops incrementing or decrementing after overflow. #1 CSOT Counter Start on Trigger 16 1 read-write 0 TPM counter starts to increment immediately, once it is enabled. #0 1 TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow. #1 DBGMODE Debug Mode 6 2 read-write 00 TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored. #00 11 TPM counter continues in debug mode. #11 DOZEEN Doze Enable 5 1 read-write 0 Internal TPM counter continues in Doze mode. #0 1 Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored. #1 GTBEEN Global time base enable 9 1 read-write 0 All channels use the internally generated TPM counter as their timebase #0 1 All channels use an externally generated global timebase as their timebase #1 GTBSYNC Global Time Base Synchronization 8 1 read-write 0 Global timebase synchronization disabled. #0 1 Global timebase synchronization enabled. #1 TRGPOL Trigger Polarity 22 1 read-write 0 Trigger is active high. #0 1 Trigger is active low. #1 TRGSEL Trigger Select 24 2 read-write TRGSRC Trigger Source 23 1 read-write 0 Trigger source selected by TRGSEL is external. #0 1 Trigger source selected by TRGSEL is internal (channel pin input capture). #1 FILTER Filter Control 0x78 32 read-write n 0x0 0x0 CH0FVAL Channel 0 Filter Value 0 4 read-write CH1FVAL Channel 1 Filter Value 4 4 read-write CH2FVAL Channel 2 Filter Value 8 4 read-write CH3FVAL Channel 3 Filter Value 12 4 read-write CH4FVAL Channel 4 Filter Value 16 4 read-write CH5FVAL Channel 5 Filter Value 20 4 read-write GLOBAL TPM Global Register 0x8 32 read-write n 0x0 0x0 RST Software Reset 1 1 read-write 0 Module is not reset. #0 1 Module is reset. #1 MOD Modulo 0x18 32 read-write n 0x0 0x0 MOD Modulo value 0 16 read-write PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 CHAN Channel Count 0 8 read-only TRIG Trigger Count 8 8 read-only WIDTH Counter Width 16 8 read-only POL Channel Polarity 0x70 32 read-write n 0x0 0x0 POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 QDCTRL Quadrature Decoder Control and Status 0x80 32 read-write n 0x0 0x0 QUADEN Enables the quadrature decoder mode 0 1 read-write 0 Quadrature decoder mode is disabled. #0 1 Quadrature decoder mode is enabled. #1 QUADIR Counter Direction in Quadrature Decode Mode 2 1 read-only 0 Counter direction is decreasing (counter decrement). #0 1 Counter direction is increasing (counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase encoding mode. #0 1 Count and direction encoding mode. #1 TOFDIR Indicates if the TOF bit was set on the top or the bottom of counting. 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero). #1 SC Status and Control 0x10 32 read-write n 0x0 0x0 CMOD Clock Mode Selection 3 2 read-write 00 TPM counter is disabled #00 01 TPM counter increments on every TPM counter clock #01 10 TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock #10 11 TPM counter increments on rising edge of the selected external input trigger. #11 CPWMS Center-Aligned PWM Select 5 1 read-write 0 TPM counter operates in up counting mode. #0 1 TPM counter operates in up-down counting mode. #1 DMA DMA Enable 8 1 read-write 0 Disables DMA transfers. #0 1 Enables DMA transfers. #1 PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 TOF Timer Overflow Flag 7 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling or DMA request. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 STATUS Capture and Compare Status 0x1C 32 read-write n 0x0 0x0 CH0F Channel 0 Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 TOF Timer Overflow Flag 8 1 read-write 0 TPM counter has not overflowed. #0 1 TPM counter has overflowed. #1 TRIG Channel Trigger 0x6C 32 read-write n 0x0 0x0 TRIG0 Channel 0 Trigger 0 1 read-write 0 No effect. #0 1 The input trigger is used for input capture and modulates output (for output compare and PWM). #1 TRIG1 Channel 1 Trigger 1 1 read-write 0 No effect. #0 1 The input trigger is used for input capture and modulates output (for output compare and PWM). #1 TRIG2 Channel 2 Trigger 2 1 read-write 0 No effect. #0 1 The input trigger is used for input capture and modulates output (for output compare and PWM). #1 TRIG3 Channel 3 Trigger 3 1 read-write 0 No effect. #0 1 The input trigger is used for input capture and modulates output (for output compare and PWM). #1 TRIG4 Channel 4 Trigger 4 1 read-write 0 No effect. #0 1 The input trigger is used for input capture and modulates output (for output compare and PWM). #1 TRIG5 Channel 5 Trigger 5 1 read-write 0 No effect. #0 1 The input trigger is used for input capture and modulates output (for output compare and PWM). #1 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Identification Number 0 16 read-only 1 Standard feature set. #1 11 Standard feature set with Filter and Combine registers implemented. #11 111 Standard feature set with Filter, Combine and Quadrature registers implemented. #111 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only TRGMUX0 TRGMUX-0 TRGMUX 0x0 0x0 0x38 registers n TRGMUX_ADC0 TRGMUX TRGCFG Register 0x10 32 read-write n 0x0 0x0 LK Enable 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write TRGMUX_CMP0 TRGMUX TRGCFG Register 0x2C 32 read-write n 0x0 0x0 LK Enable 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write TRGMUX_CMP1 TRGMUX TRGCFG Register 0x30 32 read-write n 0x0 0x0 LK Enable 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write TRGMUX_DAC0 TRGMUX TRGCFG Register 0x34 32 read-write n 0x0 0x0 LK Enable 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write TRGMUX_DMAMUX0 TRGMUX TRGCFG Register 0x0 32 read-write n 0x0 0x0 LK Enable 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write 0 Trigger function is disabled. #0 1 Port pin trigger input is selected. #1 2 FlexIO Timer 0 input is selected. #10 4 FlexIO Timer 2 input is selected. #100 8 FlexIO Timer 6 input is selected. #1000 16 LPIT1 Channel 0 is selected #10000 32 LPSPI1 Frame is selected. #100000 33 LPSPI1 RX data is selected. #100001 17 LPIT1 Channel 1 is selected #10001 34 RTC Seconds Counter is selected. #100010 35 RTC Alarm is selected. #100011 9 FlexIO Timer 7 input is selected. #1001 18 LPIT1 Channel 2 is selected #10010 36 LPTMR0 Trigger is selected. #100100 37 LPTMR1 Trigger is selected. #100101 19 LPIT1 Channel 3 is selected #10011 38 CMP0 Output is selected. #100110 39 CMP1 Output is selected. #100111 5 FlexIO Timer 3 input is selected. #101 10 TPM0 Overflow is selected #1010 20 LPUART0 RX Data is selected. #10100 40 ADC0 Conversion A Complete is selected. #101000 41 ADC0 Conversion B Complete is selected. #101001 21 LPUART0 TX Data is selected. #10101 42 Port A Pin Trigger is selected. #101010 43 Port B Pin Trigger is selected. #101011 11 TPM0 Channel 0 is selected #1011 22 LPUART0 RX Idle is selected. #10110 44 Port C Pin Trigger is selected. #101100 45 Port D Pin Trigger is selected. #101101 23 LPUART1 RX Data is selected. #10111 46 Port E Pin Trigger is selected. #101110 47 TPM2 Overflow selected. #101111 3 FlexIO Timer 1 input is selected. #11 6 FlexIO Timer 4 input is selected. #110 12 TPM0 Channel 1 is selected #1100 24 LPUART1 TX Data is selected. #11000 48 TPM2 Channel 0 is selected. #110000 49 TPM2 Channel 1 is selected. #110001 25 LPUART1 RX Idle is selected. #11001 50 LPIT0 Channel 0 is selected. #110010 51 LPIT0 Channel 1 is selected. #110011 13 TPM1 Overflow is selected #1101 26 LPI2C0 Master STOP is selected. #11010 52 LPIT0 Channel 2 is selected. #110100 53 LPIT0 Channel 3 is selected. #110101 27 LPI2C0 Slave STOP is selected. #11011 54 USB Start-of-Frame is selected. #110110 55 LPUART2 RX Data is selected. #110111 7 FlexIO Timer 5 input is selected. #111 14 TPM1 Channel 0 is selected #1110 28 LPI2C1 Master STOP is selected. #11100 56 LPUART2 TX Data is selected. #111000 57 LPUART2 RX Idle is selected. #111001 29 LPI2C1 Slave STOP is selected. #11101 58 LPI2C2 Master STOP is selected. #111010 59 LPI2C2 Slave STOP is selected. #111011 15 TPM1 Channel 1 is selected #1111 30 LPSPI0 Frame is selected. #11110 60 LPSPI2 Frame is selected. #111100 61 LPSPI2 RX Data is selected. #111101 31 LPSPI0 RX data is selected. #11111 62 SAI TX Frame Sync selected. #111110 63 SAI RX Frame Sync is selected. #111111 TRGMUX_LPI2C2 TRGMUX TRGCFG Register 0x1C 32 read-write n 0x0 0x0 LK Enable 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write TRGMUX_LPIT0 TRGMUX TRGCFG Register 0x4 32 read-write n 0x0 0x0 LK Enable 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write 0 Trigger function is disabled. #0 1 Port pin trigger input is selected. #1 2 FlexIO Timer 0 input is selected. #10 4 FlexIO Timer 2 input is selected. #100 8 FlexIO Timer 6 input is selected. #1000 16 LPIT1 Channel 0 is selected #10000 32 LPSPI1 Frame is selected. #100000 33 LPSPI1 RX data is selected. #100001 17 LPIT1 Channel 1 is selected #10001 34 RTC Seconds Counter is selected. #100010 35 RTC Alarm is selected. #100011 9 FlexIO Timer 7 input is selected. #1001 18 LPIT1 Channel 2 is selected #10010 36 LPTMR0 Trigger is selected. #100100 37 LPTMR1 Trigger is selected. #100101 19 LPIT1 Channel 3 is selected #10011 38 CMP0 Output is selected. #100110 39 CMP1 Output is selected. #100111 5 FlexIO Timer 3 input is selected. #101 10 TPM0 Overflow is selected #1010 20 LPUART0 RX Data is selected. #10100 40 ADC0 Conversion A Complete is selected. #101000 41 ADC0 Conversion B Complete is selected. #101001 21 LPUART0 TX Data is selected. #10101 42 Port A Pin Trigger is selected. #101010 43 Port B Pin Trigger is selected. #101011 11 TPM0 Channel 0 is selected #1011 22 LPUART0 RX Idle is selected. #10110 44 Port C Pin Trigger is selected. #101100 45 Port D Pin Trigger is selected. #101101 23 LPUART1 RX Data is selected. #10111 46 Port E Pin Trigger is selected. #101110 47 TPM2 Overflow selected. #101111 3 FlexIO Timer 1 input is selected. #11 6 FlexIO Timer 4 input is selected. #110 12 TPM0 Channel 1 is selected #1100 24 LPUART1 TX Data is selected. #11000 48 TPM2 Channel 0 is selected. #110000 49 TPM2 Channel 1 is selected. #110001 25 LPUART1 RX Idle is selected. #11001 50 LPIT0 Channel 0 is selected. #110010 51 LPIT0 Channel 1 is selected. #110011 13 TPM1 Overflow is selected #1101 26 LPI2C0 Master STOP is selected. #11010 52 LPIT0 Channel 2 is selected. #110100 53 LPIT0 Channel 3 is selected. #110101 27 LPI2C0 Slave STOP is selected. #11011 54 USB Start-of-Frame is selected. #110110 55 LPUART2 RX Data is selected. #110111 7 FlexIO Timer 5 input is selected. #111 14 TPM1 Channel 0 is selected #1110 28 LPI2C1 Master STOP is selected. #11100 56 LPUART2 TX Data is selected. #111000 57 LPUART2 RX Idle is selected. #111001 29 LPI2C1 Slave STOP is selected. #11101 58 LPI2C2 Master STOP is selected. #111010 59 LPI2C2 Slave STOP is selected. #111011 15 TPM1 Channel 1 is selected #1111 30 LPSPI0 Frame is selected. #11110 60 LPSPI2 Frame is selected. #111100 61 LPSPI2 RX Data is selected. #111101 31 LPSPI0 RX data is selected. #11111 62 SAI TX Frame Sync selected. #111110 63 SAI RX Frame Sync is selected. #111111 TRGMUX_LPSPI2 TRGMUX TRGCFG Register 0x24 32 read-write n 0x0 0x0 LK Enable 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write TRGMUX_LPUART2 TRGMUX TRGCFG Register 0x14 32 read-write n 0x0 0x0 LK Enable 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write TRGMUX_TPM2 TRGMUX TRGCFG Register 0x8 32 read-write n 0x0 0x0 LK Enable 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write TRGMUX1 TRGMUX-1 TRGMUX 0x0 0x0 0x2C registers n TRGMUX_DMAMUX1 TRGMUX TRGCFG Register 0x0 32 read-write n 0x0 0x0 LK Enable 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write 0 Trigger function is disabled. #0 1 Port pin trigger input is selected. #1 2 FlexIO Timer 0 input is selected. #10 4 FlexIO Timer 2 input is selected. #100 8 FlexIO Timer 6 input is selected. #1000 16 LPIT1 Channel 0 is selected #10000 32 LPSPI1 Frame is selected. #100000 33 LPSPI1 RX data is selected. #100001 17 LPIT1 Channel 1 is selected #10001 34 RTC Seconds Counter is selected. #100010 35 RTC Alarm is selected. #100011 9 FlexIO Timer 7 input is selected. #1001 18 LPIT1 Channel 2 is selected #10010 36 LPTMR0 Trigger is selected. #100100 37 LPTMR1 Trigger is selected. #100101 19 LPIT1 Channel 3 is selected #10011 38 CMP0 Output is selected. #100110 39 CMP1 Output is selected. #100111 5 FlexIO Timer 3 input is selected. #101 10 TPM0 Overflow is selected #1010 20 LPUART0 RX Data is selected. #10100 40 ADC0 Conversion A Complete is selected. #101000 41 ADC0 Conversion B Complete is selected. #101001 21 LPUART0 TX Data is selected. #10101 42 Port A Pin Trigger is selected. #101010 43 Port B Pin Trigger is selected. #101011 11 TPM0 Channel 0 is selected #1011 22 LPUART0 RX Idle is selected. #10110 44 Port C Pin Trigger is selected. #101100 45 Port D Pin Trigger is selected. #101101 23 LPUART1 RX Data is selected. #10111 46 Port E Pin Trigger is selected. #101110 47 TPM2 Overflow selected. #101111 3 FlexIO Timer 1 input is selected. #11 6 FlexIO Timer 4 input is selected. #110 12 TPM0 Channel 1 is selected #1100 24 LPUART1 TX Data is selected. #11000 48 TPM2 Channel 0 is selected. #110000 49 TPM2 Channel 1 is selected. #110001 25 LPUART1 RX Idle is selected. #11001 50 LPIT0 Channel 0 is selected. #110010 51 LPIT0 Channel 1 is selected. #110011 13 TPM1 Overflow is selected #1101 26 LPI2C0 Master STOP is selected. #11010 52 LPIT0 Channel 2 is selected. #110100 53 LPIT0 Channel 3 is selected. #110101 27 LPI2C0 Slave STOP is selected. #11011 54 USB Start-of-Frame is selected. #110110 55 LPUART2 RX Data is selected. #110111 7 FlexIO Timer 5 input is selected. #111 14 TPM1 Channel 0 is selected #1110 28 LPI2C1 Master STOP is selected. #11100 56 LPUART2 TX Data is selected. #111000 57 LPUART2 RX Idle is selected. #111001 29 LPI2C1 Slave STOP is selected. #11101 58 LPI2C2 Master STOP is selected. #111010 59 LPI2C2 Slave STOP is selected. #111011 15 TPM1 Channel 1 is selected #1111 30 LPSPI0 Frame is selected. #11110 60 LPSPI2 Frame is selected. #111100 61 LPSPI2 RX Data is selected. #111101 31 LPSPI0 RX data is selected. #11111 62 SAI TX Frame Sync selected. #111110 63 SAI RX Frame Sync is selected. #111111 TRGMUX_FLEXIO TRGMUX TRGCFG Register 0x10 32 read-write n 0x0 0x0 LK Enable 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write 0 Trigger function is disabled. #0 1 Port pin trigger input is selected. #1 2 FlexIO Timer 0 input is selected. #10 4 FlexIO Timer 2 input is selected. #100 8 FlexIO Timer 6 input is selected. #1000 16 LPIT1 Channel 0 is selected #10000 32 LPSPI1 Frame is selected. #100000 33 LPSPI1 RX data is selected. #100001 17 LPIT1 Channel 1 is selected #10001 34 RTC Seconds Counter is selected. #100010 35 RTC Alarm is selected. #100011 9 FlexIO Timer 7 input is selected. #1001 18 LPIT1 Channel 2 is selected #10010 36 LPTMR0 Trigger is selected. #100100 37 LPTMR1 Trigger is selected. #100101 19 LPIT1 Channel 3 is selected #10011 38 CMP0 Output is selected. #100110 39 CMP1 Output is selected. #100111 5 FlexIO Timer 3 input is selected. #101 10 TPM0 Overflow is selected #1010 20 LPUART0 RX Data is selected. #10100 40 ADC0 Conversion A Complete is selected. #101000 41 ADC0 Conversion B Complete is selected. #101001 21 LPUART0 TX Data is selected. #10101 42 Port A Pin Trigger is selected. #101010 43 Port B Pin Trigger is selected. #101011 11 TPM0 Channel 0 is selected #1011 22 LPUART0 RX Idle is selected. #10110 44 Port C Pin Trigger is selected. #101100 45 Port D Pin Trigger is selected. #101101 23 LPUART1 RX Data is selected. #10111 46 Port E Pin Trigger is selected. #101110 47 TPM2 Overflow selected. #101111 3 FlexIO Timer 1 input is selected. #11 6 FlexIO Timer 4 input is selected. #110 12 TPM0 Channel 1 is selected #1100 24 LPUART1 TX Data is selected. #11000 48 TPM2 Channel 0 is selected. #110000 49 TPM2 Channel 1 is selected. #110001 25 LPUART1 RX Idle is selected. #11001 50 LPIT0 Channel 0 is selected. #110010 51 LPIT0 Channel 1 is selected. #110011 13 TPM1 Overflow is selected #1101 26 LPI2C0 Master STOP is selected. #11010 52 LPIT0 Channel 2 is selected. #110100 53 LPIT0 Channel 3 is selected. #110101 27 LPI2C0 Slave STOP is selected. #11011 54 USB Start-of-Frame is selected. #110110 55 LPUART2 RX Data is selected. #110111 7 FlexIO Timer 5 input is selected. #111 14 TPM1 Channel 0 is selected #1110 28 LPI2C1 Master STOP is selected. #11100 56 LPUART2 TX Data is selected. #111000 57 LPUART2 RX Idle is selected. #111001 29 LPI2C1 Slave STOP is selected. #11101 58 LPI2C2 Master STOP is selected. #111010 59 LPI2C2 Slave STOP is selected. #111011 15 TPM1 Channel 1 is selected #1111 30 LPSPI0 Frame is selected. #11110 60 LPSPI2 Frame is selected. #111100 61 LPSPI2 RX Data is selected. #111101 31 LPSPI0 RX data is selected. #11111 62 SAI TX Frame Sync selected. #111110 63 SAI RX Frame Sync is selected. #111111 TRGMUX_LPI2C0 TRGMUX TRGCFG Register 0x1C 32 read-write n 0x0 0x0 LK Enable 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write TRGMUX_LPI2C1 TRGMUX TRGCFG Register 0x20 32 read-write n 0x0 0x0 LK Enable 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write TRGMUX_LPIT1 TRGMUX TRGCFG Register 0x4 32 read-write n 0x0 0x0 LK Enable 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write 0 Trigger function is disabled. #0 1 Port pin trigger input is selected. #1 2 FlexIO Timer 0 input is selected. #10 4 FlexIO Timer 2 input is selected. #100 8 FlexIO Timer 6 input is selected. #1000 16 LPIT1 Channel 0 is selected #10000 32 LPSPI1 Frame is selected. #100000 33 LPSPI1 RX data is selected. #100001 17 LPIT1 Channel 1 is selected #10001 34 RTC Seconds Counter is selected. #100010 35 RTC Alarm is selected. #100011 9 FlexIO Timer 7 input is selected. #1001 18 LPIT1 Channel 2 is selected #10010 36 LPTMR0 Trigger is selected. #100100 37 LPTMR1 Trigger is selected. #100101 19 LPIT1 Channel 3 is selected #10011 38 CMP0 Output is selected. #100110 39 CMP1 Output is selected. #100111 5 FlexIO Timer 3 input is selected. #101 10 TPM0 Overflow is selected #1010 20 LPUART0 RX Data is selected. #10100 40 ADC0 Conversion A Complete is selected. #101000 41 ADC0 Conversion B Complete is selected. #101001 21 LPUART0 TX Data is selected. #10101 42 Port A Pin Trigger is selected. #101010 43 Port B Pin Trigger is selected. #101011 11 TPM0 Channel 0 is selected #1011 22 LPUART0 RX Idle is selected. #10110 44 Port C Pin Trigger is selected. #101100 45 Port D Pin Trigger is selected. #101101 23 LPUART1 RX Data is selected. #10111 46 Port E Pin Trigger is selected. #101110 47 TPM2 Overflow selected. #101111 3 FlexIO Timer 1 input is selected. #11 6 FlexIO Timer 4 input is selected. #110 12 TPM0 Channel 1 is selected #1100 24 LPUART1 TX Data is selected. #11000 48 TPM2 Channel 0 is selected. #110000 49 TPM2 Channel 1 is selected. #110001 25 LPUART1 RX Idle is selected. #11001 50 LPIT0 Channel 0 is selected. #110010 51 LPIT0 Channel 1 is selected. #110011 13 TPM1 Overflow is selected #1101 26 LPI2C0 Master STOP is selected. #11010 52 LPIT0 Channel 2 is selected. #110100 53 LPIT0 Channel 3 is selected. #110101 27 LPI2C0 Slave STOP is selected. #11011 54 USB Start-of-Frame is selected. #110110 55 LPUART2 RX Data is selected. #110111 7 FlexIO Timer 5 input is selected. #111 14 TPM1 Channel 0 is selected #1110 28 LPI2C1 Master STOP is selected. #11100 56 LPUART2 TX Data is selected. #111000 57 LPUART2 RX Idle is selected. #111001 29 LPI2C1 Slave STOP is selected. #11101 58 LPI2C2 Master STOP is selected. #111010 59 LPI2C2 Slave STOP is selected. #111011 15 TPM1 Channel 1 is selected #1111 30 LPSPI0 Frame is selected. #11110 60 LPSPI2 Frame is selected. #111100 61 LPSPI2 RX Data is selected. #111101 31 LPSPI0 RX data is selected. #11111 62 SAI TX Frame Sync selected. #111110 63 SAI RX Frame Sync is selected. #111111 TRGMUX_LPSPI0 TRGMUX TRGCFG Register 0x24 32 read-write n 0x0 0x0 LK Enable 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write TRGMUX_LPSPI1 TRGMUX TRGCFG Register 0x28 32 read-write n 0x0 0x0 LK Enable 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write TRGMUX_LPUART0 TRGMUX TRGCFG Register 0x14 32 read-write n 0x0 0x0 LK Enable 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write TRGMUX_LPUART1 TRGMUX TRGCFG Register 0x18 32 read-write n 0x0 0x0 LK Enable 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write TRGMUX_TPM0 TRGMUX TRGCFG Register 0x8 32 read-write n 0x0 0x0 LK Enable 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write TRGMUX_TPM1 TRGMUX TRGCFG Register 0xC 32 read-write n 0x0 0x0 LK Enable 31 1 read-write 0 Register can be written. #0 1 Register cannot be written until the next system Reset. #1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write TRNG TRNG TRNG 0x0 0x0 0xF8 registers n TRNG 46 ENT0 TRNG Entropy Read Register 0x40 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT1 TRNG Entropy Read Register 0x44 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT10 TRNG Entropy Read Register 0x68 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT11 TRNG Entropy Read Register 0x6C 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT12 TRNG Entropy Read Register 0x70 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT13 TRNG Entropy Read Register 0x74 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT14 TRNG Entropy Read Register 0x78 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT15 TRNG Entropy Read Register 0x7C 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT2 TRNG Entropy Read Register 0x48 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT3 TRNG Entropy Read Register 0x4C 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT4 TRNG Entropy Read Register 0x50 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT5 TRNG Entropy Read Register 0x54 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT6 TRNG Entropy Read Register 0x58 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT7 TRNG Entropy Read Register 0x5C 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT8 TRNG Entropy Read Register 0x60 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT9 TRNG Entropy Read Register 0x64 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only FRQCNT TRNG Frequency Count Register TRNG 0x1C 32 read-only n 0x0 0x0 FRQ_CT Frequency Count 0 22 read-only FRQMAX TRNG Frequency Count Maximum Limit Register TRNG 0x1C 32 read-write n 0x0 0x0 FRQ_MAX Frequency Counter Maximum Limit 0 22 read-write FRQMIN TRNG Frequency Count Minimum Limit Register 0x18 32 read-write n 0x0 0x0 FRQ_MIN Frequency Count Minimum Limit 0 22 read-write INT_CTRL TRNG Interrupt Control Register 0xA4 32 read-write n 0x0 0x0 ENT_VAL Same behavior as bit 0 above. 1 1 read-write 0 Same behavior as bit 0 above. #0 1 Same behavior as bit 0 above. #1 FRQ_CT_FAIL Same behavior as bit 0 above. 2 1 read-write 0 Same behavior as bit 0 above. #0 1 Same behavior as bit 0 above. #1 HW_ERR Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted. 0 1 read-write 0 Corresponding bit of INT_STATUS cleared. #0 1 Corresponding bit of INT_STATUS active. #1 UNUSED Reserved but writeable. 3 29 read-write INT_MASK TRNG Mask Register 0xA8 32 read-write n 0x0 0x0 ENT_VAL Same behavior as bit 0 above. 1 1 read-write 0 Same behavior as bit 0 above. #0 1 Same behavior as bit 0 above. #1 FRQ_CT_FAIL Same behavior as bit 0 above. 2 1 read-write 0 Same behavior as bit 0 above. #0 1 Same behavior as bit 0 above. #1 HW_ERR Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted. 0 1 read-write 0 Corresponding interrupt of INT_STATUS is masked. #0 1 Corresponding bit of INT_STATUS is active. #1 INT_STATUS TRNG Interrupt Status Register 0xAC 32 read-write n 0x0 0x0 ENT_VAL Read only: Entropy Valid 1 1 read-only 0 Busy generation entropy. Any value read is invalid. #0 1 TRNG can be stopped and entropy is valid if read. #1 FRQ_CT_FAIL Read only: Frequency Count Fail 2 1 read-write 0 No hardware nor self test frequency errors. #0 1 The frequency counter has detected a failure. #1 HW_ERR Read: Error status 0 1 read-only 0 no error #0 1 error detected. #1 MCTL TRNG Miscellaneous Control Register 0x0 32 read-write n 0x0 0x0 ENT_VAL Read only: Entropy Valid 10 1 read-only ERR Read: Error status 12 1 read-write FCT_FAIL Read only: Frequency Count Fail 8 1 read-only FCT_VAL Read only: Frequency Count Valid. Indicates that a valid frequency count may be read from FRQCNT. 9 1 read-only FOR_SCLK Force System Clock 7 1 read-write OSC_DIV Oscillator Divide 2 2 read-write 00 use ring oscillator with no divide #00 01 use ring oscillator divided-by-2 #01 10 use ring oscillator divided-by-4 #10 11 use ring oscillator divided-by-8 #11 PRGM Programming Mode Select 16 1 read-write RST_DEF Reset Defaults 6 1 write-only SAMP_MODE Sample Mode 0 2 read-write 00 use Von Neumann data into both Entropy shifter and Statistical Checker #00 01 use raw data into both Entropy shifter and Statistical Checker #01 10 use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker #10 11 undefined/reserved. #11 TRNG_ACC TRNG Access Mode 5 1 read-write TSTOP_OK TRNG_OK_TO_STOP 13 1 read-only TST_OUT Read only: Test point inside ring oscillator. 11 1 read-only UNUSED This bit is unused but write-able. Must be left as zero. 4 1 read-write PKRCNT10 TRNG Statistical Check Poker Count 1 and 0 Register 0x80 32 read-only n 0x0 0x0 PKR_0_CT Poker 0h Count 0 16 read-only PKR_1_CT Poker 1h Count 16 16 read-only PKRCNT32 TRNG Statistical Check Poker Count 3 and 2 Register 0x84 32 read-only n 0x0 0x0 PKR_2_CT Poker 2h Count 0 16 read-only PKR_3_CT Poker 3h Count 16 16 read-only PKRCNT54 TRNG Statistical Check Poker Count 5 and 4 Register 0x88 32 read-only n 0x0 0x0 PKR_4_CT Poker 4h Count 0 16 read-only PKR_5_CT Poker 5h Count 16 16 read-only PKRCNT76 TRNG Statistical Check Poker Count 7 and 6 Register 0x8C 32 read-only n 0x0 0x0 PKR_6_CT Poker 6h Count 0 16 read-only PKR_7_CT Poker 7h Count 16 16 read-only PKRCNT98 TRNG Statistical Check Poker Count 9 and 8 Register 0x90 32 read-only n 0x0 0x0 PKR_8_CT Poker 8h Count 0 16 read-only PKR_9_CT Poker 9h Count 16 16 read-only PKRCNTBA TRNG Statistical Check Poker Count B and A Register 0x94 32 read-only n 0x0 0x0 PKR_A_CT Poker Ah Count 0 16 read-only PKR_B_CT Poker Bh Count 16 16 read-only PKRCNTDC TRNG Statistical Check Poker Count D and C Register 0x98 32 read-only n 0x0 0x0 PKR_C_CT Poker Ch Count 0 16 read-only PKR_D_CT Poker Dh Count 16 16 read-only PKRCNTFE TRNG Statistical Check Poker Count F and E Register 0x9C 32 read-only n 0x0 0x0 PKR_E_CT Poker Eh Count 0 16 read-only PKR_F_CT Poker Fh Count 16 16 read-only PKRMAX TRNG Poker Maximum Limit Register TRNG 0xC 32 read-write n 0x0 0x0 PKR_MAX Poker Maximum Limit 0 24 read-write PKRRNG TRNG Poker Range Register 0x8 32 read-write n 0x0 0x0 PKR_RNG Poker Range 0 16 read-write PKRSQ TRNG Poker Square Calculation Result Register TRNG 0xC 32 read-only n 0x0 0x0 PKR_SQ Poker Square Calculation Result 0 24 read-only SBLIM TRNG Sparse Bit Limit Register TRNG 0x14 32 read-write n 0x0 0x0 SB_LIM Sparse Bit Limit 0 10 read-write SCMC TRNG Statistical Check Monobit Count Register TRNG 0x20 32 read-only n 0x0 0x0 MONO_CT Monobit Count 0 16 read-only SCMISC TRNG Statistical Check Miscellaneous Register 0x4 32 read-write n 0x0 0x0 LRUN_MAX LONG RUN MAX LIMIT 0 8 read-write RTY_CT RETRY COUNT 16 4 read-write SCML TRNG Statistical Check Monobit Limit Register TRNG 0x20 32 read-write n 0x0 0x0 MONO_MAX Monobit Maximum Limit 0 16 read-write MONO_RNG Monobit Range 16 16 read-write SCR1C TRNG Statistical Check Run Length 1 Count Register TRNG 0x24 32 read-only n 0x0 0x0 R1_0_CT Runs of Zero, Length 1 Count 0 15 read-only R1_1_CT Runs of One, Length 1 Count 16 15 read-only SCR1L TRNG Statistical Check Run Length 1 Limit Register TRNG 0x24 32 read-write n 0x0 0x0 RUN1_MAX Run Length 1 Maximum Limit 0 15 read-write RUN1_RNG Run Length 1 Range 16 15 read-write SCR2C TRNG Statistical Check Run Length 2 Count Register TRNG 0x28 32 read-only n 0x0 0x0 R2_0_CT Runs of Zero, Length 2 Count 0 14 read-only R2_1_CT Runs of One, Length 2 Count 16 14 read-only SCR2L TRNG Statistical Check Run Length 2 Limit Register TRNG 0x28 32 read-write n 0x0 0x0 RUN2_MAX Run Length 2 Maximum Limit 0 14 read-write RUN2_RNG Run Length 2 Range 16 14 read-write SCR3C TRNG Statistical Check Run Length 3 Count Register TRNG 0x2C 32 read-only n 0x0 0x0 R3_0_CT Runs of Zeroes, Length 3 Count 0 13 read-only R3_1_CT Runs of Ones, Length 3 Count 16 13 read-only SCR3L TRNG Statistical Check Run Length 3 Limit Register TRNG 0x2C 32 read-write n 0x0 0x0 RUN3_MAX Run Length 3 Maximum Limit 0 13 read-write RUN3_RNG Run Length 3 Range 16 13 read-write SCR4C TRNG Statistical Check Run Length 4 Count Register TRNG 0x30 32 read-only n 0x0 0x0 R4_0_CT Runs of Zero, Length 4 Count 0 12 read-only R4_1_CT Runs of One, Length 4 Count 16 12 read-only SCR4L TRNG Statistical Check Run Length 4 Limit Register TRNG 0x30 32 read-write n 0x0 0x0 RUN4_MAX Run Length 4 Maximum Limit 0 12 read-write RUN4_RNG Run Length 4 Range 16 12 read-write SCR5C TRNG Statistical Check Run Length 5 Count Register TRNG 0x34 32 read-only n 0x0 0x0 R5_0_CT Runs of Zero, Length 5 Count 0 11 read-only R5_1_CT Runs of One, Length 5 Count 16 11 read-only SCR5L TRNG Statistical Check Run Length 5 Limit Register TRNG 0x34 32 read-write n 0x0 0x0 RUN5_MAX Run Length 5 Maximum Limit 0 11 read-write RUN5_RNG Run Length 5 Range 16 11 read-write SCR6PC TRNG Statistical Check Run Length 6+ Count Register TRNG 0x38 32 read-only n 0x0 0x0 R6P_0_CT Runs of Zero, Length 6+ Count 0 11 read-only R6P_1_CT Runs of One, Length 6+ Count 16 11 read-only SCR6PL TRNG Statistical Check Run Length 6+ Limit Register TRNG 0x38 32 read-write n 0x0 0x0 RUN6P_MAX Run Length 6+ Maximum Limit 0 11 read-write RUN6P_RNG Run Length 6+ Range 16 11 read-write SDCTL TRNG Seed Control Register 0x10 32 read-write n 0x0 0x0 ENT_DLY Entropy Delay 16 16 read-write SAMP_SIZE Sample Size 0 16 read-write SEC_CFG TRNG Security Configuration Register 0xA0 32 read-write n 0x0 0x0 NO_PRGM If set, the TRNG registers cannot be programmed 1 1 read-write 0 Programability of registers controlled only by the TRNG Miscellaneous Control Register's access mode bit. #0 1 Overides TRNG Miscellaneous Control Register access mode and prevents TRNG register programming. #1 SH0 Reserved. DRNG specific, not applicable to this version. 0 1 read-write 0 See DRNG version. #0 1 See DRNG version. #1 SK_VAL Reserved. DRNG-specific, not applicable to this version. 2 1 read-write 0 See DRNG version. #0 1 See DRNG version. #1 STATUS TRNG Status Register 0x3C 32 read-only n 0x0 0x0 RETRY_CT RETRY COUNT 16 4 read-only TF1BR0 Test Fail, 1-Bit Run, Sampling 0s. If TF1BR0=1, the 1-Bit Run, Sampling 0s Test has failed. 0 1 read-only TF1BR1 Test Fail, 1-Bit Run, Sampling 1s. If TF1BR1=1, the 1-Bit Run, Sampling 1s Test has failed. 1 1 read-only TF2BR0 Test Fail, 2-Bit Run, Sampling 0s. If TF2BR0=1, the 2-Bit Run, Sampling 0s Test has failed. 2 1 read-only TF2BR1 Test Fail, 2-Bit Run, Sampling 1s. If TF2BR1=1, the 2-Bit Run, Sampling 1s Test has failed. 3 1 read-only TF3BR0 Test Fail, 3-Bit Run, Sampling 0s. If TF3BR0=1, the 3-Bit Run, Sampling 0s Test has failed. 4 1 read-only TF3BR1 Test Fail, 3-Bit Run, Sampling 1s. If TF3BR1=1, the 3-Bit Run, Sampling 1s Test has failed. 5 1 read-only TF4BR0 Test Fail, 4-Bit Run, Sampling 0s. If TF4BR0=1, the 4-Bit Run, Sampling 0s Test has failed. 6 1 read-only TF4BR1 Test Fail, 4-Bit Run, Sampling 1s. If TF4BR1=1, the 4-Bit Run, Sampling 1s Test has failed. 7 1 read-only TF5BR0 Test Fail, 5-Bit Run, Sampling 0s. If TF5BR0=1, the 5-Bit Run, Sampling 0s Test has failed. 8 1 read-only TF5BR1 Test Fail, 5-Bit Run, Sampling 1s. If TF5BR1=1, the 5-Bit Run, Sampling 1s Test has failed. 9 1 read-only TF6PBR0 Test Fail, 6 Plus Bit Run, Sampling 0s 10 1 read-only TF6PBR1 Test Fail, 6 Plus Bit Run, Sampling 1s 11 1 read-only TFLR Test Fail, Long Run. If TFLR=1, the Long Run Test has failed. 13 1 read-only TFMB Test Fail, Mono Bit. If TFMB=1, the Mono Bit Test has failed. 15 1 read-only TFP Test Fail, Poker. If TFP=1, the Poker Test has failed. 14 1 read-only TFSB Test Fail, Sparse Bit. If TFSB=1, the Sparse Bit Test has failed. 12 1 read-only TOTSAM TRNG Total Samples Register TRNG 0x14 32 read-only n 0x0 0x0 TOT_SAM Total Samples 0 20 read-only VID1 TRNG Version ID Register (MS) 0xF0 32 read-only n 0x0 0x0 IP_ID Shows the Freescale IP ID. 16 16 read-only 0x0030 ID for TRNG. #110000 MAJ_REV Shows the Freescale IP's Major revision of the TRNG. 8 8 read-only 0x01 Major revision number for TRNG. #1 MIN_REV Shows the Freescale IP's Minor revision of the TRNG. 0 8 read-only 0x00 Minor revision number for TRNG. #0 VID2 TRNG Version ID Register (LS) 0xF4 32 read-only n 0x0 0x0 CONFIG_OPT Shows the Freescale IP's Configuaration options for the TRNG. 0 8 read-only 0x00 TRNG_CONFIG_OPT for TRNG. #0 ECO_REV Shows the Freescale IP's ECO revision of the TRNG. 8 8 read-only 0x00 TRNG_ECO_REV for TRNG. #0 ERA Shows the Freescale compile options for the TRNG. 24 8 read-only 0x00 COMPILE_OPT for TRNG. #0 INTG_OPT Shows the Freescale integration options for the TRNG. 16 8 read-only 0x00 INTG_OPT for TRNG. #0 TSI0 Touch sense input TSI0 0x0 0x0 0xC registers n TSI0 40 DATA TSI DATA Register 0x4 32 read-write n 0x0 0x0 DMAEN DMA Transfer Enabled 23 1 read-write 0 Interrupt is selected when the interrupt enable bit is set and the corresponding TSI events assert. #0 1 DMA transfer request is selected when the interrupt enable bit is set and the corresponding TSI events assert. #1 SWTS Software Trigger Start 22 1 write-only 0 No effect. #0 1 Start a scan to determine which channel is specified by TSI_DATA[TSICH]. #1 TSICH TSICH 28 4 read-write 0000 Channel 0. #0000 0001 Channel 1. #0001 0010 Channel 2. #0010 0011 Channel 3. #0011 0100 Channel 4. #0100 0101 Channel 5. #0101 0110 Channel 6. #0110 0111 Channel 7. #0111 1000 Channel 8. #1000 1001 Channel 9. #1001 1010 Channel 10. #1010 1011 Channel 11. #1011 1100 Channel 12. #1100 1101 Channel 13. #1101 1110 Channel 14. #1110 1111 Channel 15. #1111 TSICNT TSI Conversion Counter Value 0 16 read-only GENCS TSI General Control and Status Register 0x0 32 read-write n 0x0 0x0 CURSW CURSW 1 1 read-write 0 The current source pair are not swapped. #0 1 The current source pair are swapped. #1 DVOLT DVOLT 19 2 read-write 00 DV = 1.026 V; VP = 1.328 V; Vm = 0.302 V. #00 01 DV = 0.592 V; VP = 1.111 V; Vm = 0.519 V. #01 10 DV = 0.342 V; VP = 0.986 V; Vm = 0.644 V. #10 11 DV = 0.197 V; VP = 0.914 V; Vm = 0.716 V. #11 EOSDMEO End-of-Scan DMA Transfer Request Enable Only 0 1 read-write 0 Do not enable the End-of-Scan DMA transfer request only. Depending on ESOR state, either Out-of-Range or End-of-Scan can trigger a DMA transfer request and interrupt. #0 1 Only the End-of-Scan event can trigger a DMA transfer request. The Out-of-Range event only and always triggers an interrupt if TSIIE is set. #1 EOSF End of Scan Flag 2 1 read-write 0 Scan not complete. #0 1 Scan complete. #1 ESOR End-of-scan or Out-of-Range Interrupt Selection 28 1 read-write 0 Out-of-range interrupt is allowed. #0 1 End-of-scan interrupt is allowed. #1 EXTCHRG EXTCHRG 16 3 read-write 000 500 nA. #000 001 1 uA. #001 010 2 uA. #010 011 4 uA. #011 100 8 uA. #100 101 16 uA. #101 110 32 uA. #110 111 64 uA. #111 MODE TSI analog modes setup and status bits. 24 4 read-write 0000 Set TSI in capacitive sensing(non-noise detection) mode. #0000 0100 Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is disabled. #0100 1000 Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is enabled to work in higher frequencies operations. #1000 1100 Set TSI analog to work in automatic noise detection mode. #1100 NSCN NSCN 8 5 read-write 00000 Once per electrode #00000 00001 Twice per electrode #00001 00010 3 times per electrode #00010 00011 4 times per electrode #00011 00100 5 times per electrode #00100 00101 6 times per electrode #00101 00110 7 times per electrode #00110 00111 8 times per electrode #00111 01000 9 times per electrode #01000 01001 10 times per electrode #01001 01010 11 times per electrode #01010 01011 12 times per electrode #01011 01100 13 times per electrode #01100 01101 14 times per electrode #01101 01110 15 times per electrode #01110 01111 16 times per electrode #01111 10000 17 times per electrode #10000 10001 18 times per electrode #10001 10010 19 times per electrode #10010 10011 20 times per electrode #10011 10100 21 times per electrode #10100 10101 22 times per electrode #10101 10110 23 times per electrode #10110 10111 24 times per electrode #10111 11000 25 times per electrode #11000 11001 26 times per electrode #11001 11010 27 times per electrode #11010 11011 28 times per electrode #11011 11100 29 times per electrode #11100 11101 30 times per electrode #11101 11110 31 times per electrode #11110 11111 32 times per electrode #11111 OUTRGF Out of Range Flag. 31 1 read-write PS PS 13 3 read-write 000 Electrode Oscillator Frequency divided by 1 #000 001 Electrode Oscillator Frequency divided by 2 #001 010 Electrode Oscillator Frequency divided by 4 #010 011 Electrode Oscillator Frequency divided by 8 #011 100 Electrode Oscillator Frequency divided by 16 #100 101 Electrode Oscillator Frequency divided by 32 #101 110 Electrode Oscillator Frequency divided by 64 #110 111 Electrode Oscillator Frequency divided by 128 #111 REFCHRG REFCHRG 21 3 read-write 000 500 nA. #000 001 1 uA. #001 010 2 uA. #010 011 4 uA. #011 100 8 uA. #100 101 16 uA. #101 110 32 uA. #110 111 64 uA. #111 SCNIP Scan In Progress Status 3 1 read-only 0 No scan in progress. #0 1 Scan in progress. #1 STM Scan Trigger Mode 4 1 read-write 0 Software trigger scan. #0 1 Hardware trigger scan. #1 STPE TSI STOP Enable 5 1 read-write 0 TSI is disabled when MCU goes into low power mode. #0 1 Allows TSI to continue running in all low power modes. #1 TSIEN Touch Sensing Input Module Enable 7 1 read-write 0 TSI module disabled. #0 1 TSI module enabled. #1 TSIIEN Touch Sensing Input Interrupt Enable 6 1 read-write 0 TSI interrupt is disabled. #0 1 TSI interrupt is enabled. #1 TSHD TSI Threshold Register 0x8 32 read-write n 0x0 0x0 THRESH TSI Wakeup Channel High-threshold 16 16 read-write THRESL TSI Wakeup Channel Low-threshold 0 16 read-write TSTMR0 Timestamp Timer TSTMR 0x0 0x0 0x8 registers n H Time Stamp Timer Register High 0x4 32 read-only n 0x0 0x0 VALUE Time Stamp Timer High 0 24 read-only L Time Stamp Timer Register Low 0x0 32 read-only n 0x0 0x0 VALUE Time Stamp Timer Low 0 32 read-only TSTMR1 Timestamp Timer TSTMR 0x0 0x0 0x8 registers n H Time Stamp Timer Register High 0x4 32 read-only n 0x0 0x0 VALUE Time Stamp Timer High 0 24 read-only L Time Stamp Timer Register Low 0x0 32 read-only n 0x0 0x0 VALUE Time Stamp Timer Low 0 32 read-only USB0 Universal Serial Bus, OTG Capable Controller USB0 0x0 0x0 0x15D registers n USB0 24 ADDINFO Peripheral Additional Info register 0xC 8 read-only n 0x0 0x0 IEHOST This bit is set if host mode is enabled. 0 1 read-only ADDR Address register 0x98 8 read-write n 0x0 0x0 ADDR USB Address 0 7 read-write LSEN Low Speed Enable bit 7 1 read-write BDTPAGE1 BDT Page register 1 0x9C 8 read-write n 0x0 0x0 BDTBA Provides address bits 15 through 9 of the BDT base address. 1 7 read-write BDTPAGE2 BDT Page Register 2 0xB0 8 read-write n 0x0 0x0 BDTBA Provides address bits 23 through 16 of the BDT base address that defines the location of Buffer Descriptor Table resides in system memory 0 8 read-write BDTPAGE3 BDT Page Register 3 0xB4 8 read-write n 0x0 0x0 BDTBA Provides address bits 31 through 24 of the BDT base address that defines the location of Buffer Descriptor Table resides in system memory 0 8 read-write CLK_RECOVER_CTRL USB Clock recovery control 0x140 8 read-write n 0x0 0x0 CLOCK_RECOVER_EN Crystal-less USB enable 7 1 read-write 0 Disable clock recovery block (default) #0 1 Enable clock recovery block #1 RESET_RESUME_ROUGH_EN Reset/resume to rough phase enable 6 1 read-write 0 Always works in tracking phase after the first time rough to track transition (default) #0 1 Go back to rough stage whenever bus reset or bus resume occurs #1 RESTART_IFRTRIM_EN Restart from IFR trim value 5 1 read-write 0 Trim fine adjustment always works based on the previous updated trim fine value (default) #0 1 Trim fine restarts from the IFR trim value whenever bus_reset/bus_resume is detected or module enable is desasserted #1 CLK_RECOVER_INT_EN Clock recovery combined interrupt enable 0x154 8 read-write n 0x0 0x0 OVF_ERROR_EN Determines whether OVF_ERROR condition signal is used in generation of USB_CLK_RECOVERY_INT. 4 1 read-write 0 The interrupt will be masked #0 1 The interrupt will be enabled (default) #1 CLK_RECOVER_INT_STATUS Clock recovery separated interrupt status 0x15C 8 read-write n 0x0 0x0 OVF_ERROR Indicates that the USB clock recovery algorithm has detected that the frequency trim adjustment needed for the FIRC output clock is outside the available TRIM_FINE adjustment range for the FIRC module 4 1 read-write 0 No interrupt is reported #0 1 Unmasked interrupt has been generated #1 CONTROL USB OTG Control register 0x108 8 read-write n 0x0 0x0 DPPULLUPNONOTG Provides control of the DP Pullup in USBOTG, if USB is configured in non-OTG device mode. 4 1 read-write 0 DP Pullup in non-OTG device mode is not enabled. #0 1 DP Pullup in non-OTG device mode is enabled. #1 CTL Control register 0x94 8 read-write n 0x0 0x0 HOSTMODEEN When set to 1, this bit enables the USB Module to operate in Host mode 3 1 read-write JSTATE Live USB differential receiver JSTATE signal 7 1 read-write ODDRST Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0, which then specifies the EVEN BDT bank 1 1 read-write RESET Setting this bit enables the USB Module to generate USB reset signaling 4 1 read-write RESUME When set to 1 this bit enables the USB Module to execute resume signaling 2 1 read-write SE0 Live USB Single Ended Zero signal 6 1 read-write TXSUSPENDTOKENBUSY In Host mode, TOKEN_BUSY is set when the USB module is busy executing a USB token 5 1 read-write USBENSOFEN USB Enable 0 1 read-write 0 Disables the USB Module. #0 1 Enables the USB Module. #1 ENDPT0 Endpoint Control register 0x180 8 read-write n 0x0 0x0 EPCTLDIS This bit, when set, disables control (SETUP) transfers 4 1 read-write EPHSHK When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint 0 1 read-write EPRXEN This bit, when set, enables the endpoint for RX transfers. See 3 1 read-write EPSTALL When set, this bit indicates that the endpoint is stalled 1 1 read-write EPTXEN This bit, when set, enables the endpoint for TX transfers. See 2 1 read-write HOSTWOHUB Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only 7 1 read-write 0 Low-speed device connected to Host through a hub. PRE_PID will be generated as required. #0 1 Low-speed device directly connected. No hub, or no low-speed device attached. #1 RETRYDIS This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only 6 1 read-write ENDPT1 Endpoint Control register 0x244 8 read-write n 0x0 0x0 EPCTLDIS This bit, when set, disables control (SETUP) transfers 4 1 read-write EPHSHK When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint 0 1 read-write EPRXEN This bit, when set, enables the endpoint for RX transfers. See 3 1 read-write EPSTALL When set, this bit indicates that the endpoint is stalled 1 1 read-write EPTXEN This bit, when set, enables the endpoint for TX transfers. See 2 1 read-write HOSTWOHUB Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only 7 1 read-write 0 Low-speed device connected to Host through a hub. PRE_PID will be generated as required. #0 1 Low-speed device directly connected. No hub, or no low-speed device attached. #1 RETRYDIS This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only 6 1 read-write ENDPT10 Endpoint Control register 0x9DC 8 read-write n 0x0 0x0 EPCTLDIS This bit, when set, disables control (SETUP) transfers 4 1 read-write EPHSHK When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint 0 1 read-write EPRXEN This bit, when set, enables the endpoint for RX transfers. See 3 1 read-write EPSTALL When set, this bit indicates that the endpoint is stalled 1 1 read-write EPTXEN This bit, when set, enables the endpoint for TX transfers. See 2 1 read-write HOSTWOHUB Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only 7 1 read-write 0 Low-speed device connected to Host through a hub. PRE_PID will be generated as required. #0 1 Low-speed device directly connected. No hub, or no low-speed device attached. #1 RETRYDIS This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only 6 1 read-write ENDPT11 Endpoint Control register 0xAC8 8 read-write n 0x0 0x0 EPCTLDIS This bit, when set, disables control (SETUP) transfers 4 1 read-write EPHSHK When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint 0 1 read-write EPRXEN This bit, when set, enables the endpoint for RX transfers. See 3 1 read-write EPSTALL When set, this bit indicates that the endpoint is stalled 1 1 read-write EPTXEN This bit, when set, enables the endpoint for TX transfers. See 2 1 read-write HOSTWOHUB Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only 7 1 read-write 0 Low-speed device connected to Host through a hub. PRE_PID will be generated as required. #0 1 Low-speed device directly connected. No hub, or no low-speed device attached. #1 RETRYDIS This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only 6 1 read-write ENDPT12 Endpoint Control register 0xBB8 8 read-write n 0x0 0x0 EPCTLDIS This bit, when set, disables control (SETUP) transfers 4 1 read-write EPHSHK When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint 0 1 read-write EPRXEN This bit, when set, enables the endpoint for RX transfers. See 3 1 read-write EPSTALL When set, this bit indicates that the endpoint is stalled 1 1 read-write EPTXEN This bit, when set, enables the endpoint for TX transfers. See 2 1 read-write HOSTWOHUB Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only 7 1 read-write 0 Low-speed device connected to Host through a hub. PRE_PID will be generated as required. #0 1 Low-speed device directly connected. No hub, or no low-speed device attached. #1 RETRYDIS This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only 6 1 read-write ENDPT13 Endpoint Control register 0xCAC 8 read-write n 0x0 0x0 EPCTLDIS This bit, when set, disables control (SETUP) transfers 4 1 read-write EPHSHK When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint 0 1 read-write EPRXEN This bit, when set, enables the endpoint for RX transfers. See 3 1 read-write EPSTALL When set, this bit indicates that the endpoint is stalled 1 1 read-write EPTXEN This bit, when set, enables the endpoint for TX transfers. See 2 1 read-write HOSTWOHUB Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only 7 1 read-write 0 Low-speed device connected to Host through a hub. PRE_PID will be generated as required. #0 1 Low-speed device directly connected. No hub, or no low-speed device attached. #1 RETRYDIS This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only 6 1 read-write ENDPT14 Endpoint Control register 0xDA4 8 read-write n 0x0 0x0 EPCTLDIS This bit, when set, disables control (SETUP) transfers 4 1 read-write EPHSHK When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint 0 1 read-write EPRXEN This bit, when set, enables the endpoint for RX transfers. See 3 1 read-write EPSTALL When set, this bit indicates that the endpoint is stalled 1 1 read-write EPTXEN This bit, when set, enables the endpoint for TX transfers. See 2 1 read-write HOSTWOHUB Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only 7 1 read-write 0 Low-speed device connected to Host through a hub. PRE_PID will be generated as required. #0 1 Low-speed device directly connected. No hub, or no low-speed device attached. #1 RETRYDIS This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only 6 1 read-write ENDPT15 Endpoint Control register 0xEA0 8 read-write n 0x0 0x0 EPCTLDIS This bit, when set, disables control (SETUP) transfers 4 1 read-write EPHSHK When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint 0 1 read-write EPRXEN This bit, when set, enables the endpoint for RX transfers. See 3 1 read-write EPSTALL When set, this bit indicates that the endpoint is stalled 1 1 read-write EPTXEN This bit, when set, enables the endpoint for TX transfers. See 2 1 read-write HOSTWOHUB Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only 7 1 read-write 0 Low-speed device connected to Host through a hub. PRE_PID will be generated as required. #0 1 Low-speed device directly connected. No hub, or no low-speed device attached. #1 RETRYDIS This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only 6 1 read-write ENDPT2 Endpoint Control register 0x30C 8 read-write n 0x0 0x0 EPCTLDIS This bit, when set, disables control (SETUP) transfers 4 1 read-write EPHSHK When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint 0 1 read-write EPRXEN This bit, when set, enables the endpoint for RX transfers. See 3 1 read-write EPSTALL When set, this bit indicates that the endpoint is stalled 1 1 read-write EPTXEN This bit, when set, enables the endpoint for TX transfers. See 2 1 read-write HOSTWOHUB Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only 7 1 read-write 0 Low-speed device connected to Host through a hub. PRE_PID will be generated as required. #0 1 Low-speed device directly connected. No hub, or no low-speed device attached. #1 RETRYDIS This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only 6 1 read-write ENDPT3 Endpoint Control register 0x3D8 8 read-write n 0x0 0x0 EPCTLDIS This bit, when set, disables control (SETUP) transfers 4 1 read-write EPHSHK When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint 0 1 read-write EPRXEN This bit, when set, enables the endpoint for RX transfers. See 3 1 read-write EPSTALL When set, this bit indicates that the endpoint is stalled 1 1 read-write EPTXEN This bit, when set, enables the endpoint for TX transfers. See 2 1 read-write HOSTWOHUB Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only 7 1 read-write 0 Low-speed device connected to Host through a hub. PRE_PID will be generated as required. #0 1 Low-speed device directly connected. No hub, or no low-speed device attached. #1 RETRYDIS This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only 6 1 read-write ENDPT4 Endpoint Control register 0x4A8 8 read-write n 0x0 0x0 EPCTLDIS This bit, when set, disables control (SETUP) transfers 4 1 read-write EPHSHK When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint 0 1 read-write EPRXEN This bit, when set, enables the endpoint for RX transfers. See 3 1 read-write EPSTALL When set, this bit indicates that the endpoint is stalled 1 1 read-write EPTXEN This bit, when set, enables the endpoint for TX transfers. See 2 1 read-write HOSTWOHUB Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only 7 1 read-write 0 Low-speed device connected to Host through a hub. PRE_PID will be generated as required. #0 1 Low-speed device directly connected. No hub, or no low-speed device attached. #1 RETRYDIS This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only 6 1 read-write ENDPT5 Endpoint Control register 0x57C 8 read-write n 0x0 0x0 EPCTLDIS This bit, when set, disables control (SETUP) transfers 4 1 read-write EPHSHK When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint 0 1 read-write EPRXEN This bit, when set, enables the endpoint for RX transfers. See 3 1 read-write EPSTALL When set, this bit indicates that the endpoint is stalled 1 1 read-write EPTXEN This bit, when set, enables the endpoint for TX transfers. See 2 1 read-write HOSTWOHUB Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only 7 1 read-write 0 Low-speed device connected to Host through a hub. PRE_PID will be generated as required. #0 1 Low-speed device directly connected. No hub, or no low-speed device attached. #1 RETRYDIS This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only 6 1 read-write ENDPT6 Endpoint Control register 0x654 8 read-write n 0x0 0x0 EPCTLDIS This bit, when set, disables control (SETUP) transfers 4 1 read-write EPHSHK When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint 0 1 read-write EPRXEN This bit, when set, enables the endpoint for RX transfers. See 3 1 read-write EPSTALL When set, this bit indicates that the endpoint is stalled 1 1 read-write EPTXEN This bit, when set, enables the endpoint for TX transfers. See 2 1 read-write HOSTWOHUB Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only 7 1 read-write 0 Low-speed device connected to Host through a hub. PRE_PID will be generated as required. #0 1 Low-speed device directly connected. No hub, or no low-speed device attached. #1 RETRYDIS This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only 6 1 read-write ENDPT7 Endpoint Control register 0x730 8 read-write n 0x0 0x0 EPCTLDIS This bit, when set, disables control (SETUP) transfers 4 1 read-write EPHSHK When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint 0 1 read-write EPRXEN This bit, when set, enables the endpoint for RX transfers. See 3 1 read-write EPSTALL When set, this bit indicates that the endpoint is stalled 1 1 read-write EPTXEN This bit, when set, enables the endpoint for TX transfers. See 2 1 read-write HOSTWOHUB Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only 7 1 read-write 0 Low-speed device connected to Host through a hub. PRE_PID will be generated as required. #0 1 Low-speed device directly connected. No hub, or no low-speed device attached. #1 RETRYDIS This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only 6 1 read-write ENDPT8 Endpoint Control register 0x810 8 read-write n 0x0 0x0 EPCTLDIS This bit, when set, disables control (SETUP) transfers 4 1 read-write EPHSHK When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint 0 1 read-write EPRXEN This bit, when set, enables the endpoint for RX transfers. See 3 1 read-write EPSTALL When set, this bit indicates that the endpoint is stalled 1 1 read-write EPTXEN This bit, when set, enables the endpoint for TX transfers. See 2 1 read-write HOSTWOHUB Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only 7 1 read-write 0 Low-speed device connected to Host through a hub. PRE_PID will be generated as required. #0 1 Low-speed device directly connected. No hub, or no low-speed device attached. #1 RETRYDIS This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only 6 1 read-write ENDPT9 Endpoint Control register 0x8F4 8 read-write n 0x0 0x0 EPCTLDIS This bit, when set, disables control (SETUP) transfers 4 1 read-write EPHSHK When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint 0 1 read-write EPRXEN This bit, when set, enables the endpoint for RX transfers. See 3 1 read-write EPSTALL When set, this bit indicates that the endpoint is stalled 1 1 read-write EPTXEN This bit, when set, enables the endpoint for TX transfers. See 2 1 read-write HOSTWOHUB Host without a hub This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only 7 1 read-write 0 Low-speed device connected to Host through a hub. PRE_PID will be generated as required. #0 1 Low-speed device directly connected. No hub, or no low-speed device attached. #1 RETRYDIS This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only 6 1 read-write ERREN Error Interrupt Enable register 0x8C 8 read-write n 0x0 0x0 BTOERREN BTOERR Interrupt Enable 4 1 read-write 0 Disables the BTOERR interrupt. #0 1 Enables the BTOERR interrupt. #1 BTSERREN BTSERR Interrupt Enable 7 1 read-write 0 Disables the BTSERR interrupt. #0 1 Enables the BTSERR interrupt. #1 CRC16EN CRC16 Interrupt Enable 2 1 read-write 0 Disables the CRC16 interrupt. #0 1 Enables the CRC16 interrupt. #1 CRC5EOFEN CRC5/EOF Interrupt Enable 1 1 read-write 0 Disables the CRC5/EOF interrupt. #0 1 Enables the CRC5/EOF interrupt. #1 DFN8EN DFN8 Interrupt Enable 3 1 read-write 0 Disables the DFN8 interrupt. #0 1 Enables the DFN8 interrupt. #1 DMAERREN DMAERR Interrupt Enable 5 1 read-write 0 Disables the DMAERR interrupt. #0 1 Enables the DMAERR interrupt. #1 OWNERREN OWNERR Interrupt Enable 6 1 read-write 0 Disables the OWNERR interrupt. #0 1 Enables the OWNERR interrupt. #1 PIDERREN PIDERR Interrupt Enable 0 1 read-write 0 Disables the PIDERR interrupt. #0 1 Enters the PIDERR interrupt. #1 ERRSTAT Error Interrupt Status register 0x88 8 read-write n 0x0 0x0 BTOERR This bit is set when a bus turnaround timeout error occurs 4 1 read-write BTSERR This bit is set when a bit stuff error is detected 7 1 read-write CRC16 This bit is set when a data packet is rejected due to a CRC16 error. 2 1 read-write CRC5EOF This error interrupt has two functions 1 1 read-write DFN8 This bit is set if the data field received was not 8 bits in length 3 1 read-write DMAERR This bit is set if the USB Module has requested a DMA access to read a new BDT but has not been given the bus before it needs to receive or transmit data 5 1 read-write OWNERR This field is valid when the USB Module is operating in peripheral mode (CTL[HOSTMODEEN]=0) 6 1 read-write PIDERR This bit is set when the PID check field fails. 0 1 read-write FRMNUMH Frame Number register High 0xA4 8 read-write n 0x0 0x0 FRM This 3-bit field and the 8-bit field in the Frame Number Register Low are used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory 0 3 read-write FRMNUML Frame Number register Low 0xA0 8 read-write n 0x0 0x0 FRM This 8-bit field and the 3-bit field in the Frame Number Register High are used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory 0 8 read-write IDCOMP Peripheral ID Complement register 0x4 8 read-only n 0x0 0x0 NID Ones' complement of PERID[ID] bits. 0 6 read-only INTEN Interrupt Enable register 0x84 8 read-write n 0x0 0x0 ATTACHEN ATTACH Interrupt Enable 6 1 read-write 0 Disables the ATTACH interrupt. #0 1 Enables the ATTACH interrupt. #1 ERROREN ERROR Interrupt Enable 1 1 read-write 0 Disables the ERROR interrupt. #0 1 Enables the ERROR interrupt. #1 RESUMEEN RESUME Interrupt Enable 5 1 read-write 0 Disables the RESUME interrupt. #0 1 Enables the RESUME interrupt. #1 SLEEPEN SLEEP Interrupt Enable 4 1 read-write 0 Disables the SLEEP interrupt. #0 1 Enables the SLEEP interrupt. #1 SOFTOKEN SOFTOK Interrupt Enable 2 1 read-write 0 Disbles the SOFTOK interrupt. #0 1 Enables the SOFTOK interrupt. #1 STALLEN STALL Interrupt Enable 7 1 read-write 0 Diasbles the STALL interrupt. #0 1 Enables the STALL interrupt. #1 TOKDNEEN TOKDNE Interrupt Enable 3 1 read-write 0 Disables the TOKDNE interrupt. #0 1 Enables the TOKDNE interrupt. #1 USBRSTEN USBRST Interrupt Enable 0 1 read-write 0 Disables the USBRST interrupt. #0 1 Enables the USBRST interrupt. #1 ISTAT Interrupt Status register 0x80 8 read-write n 0x0 0x0 ATTACH Attach Interrupt 6 1 read-write 0 No Attach is detected since the last time the ATTACH bit was cleared. #0 1 A peripheral is now present and must be configured (a stable non-SE0 state is detected for more than 2.5 us). #1 ERROR This bit is set when any of the error conditions within Error Interrupt Status (ERRSTAT) register occur 1 1 read-write RESUME This bit is set when a K-state is observed on the DP/DM signals for 2 5 1 read-write SLEEP This bit is set when the USB Module detects a constant idle on the USB bus for 3 ms 4 1 read-write SOFTOK This bit is set when the USB Module receives a Start Of Frame (SOF) token 2 1 read-write STALL Stall Interrupt 7 1 read-write TOKDNE This bit is set when the current token being processed has completed 3 1 read-write USBRST This bit is set when the USB Module has decoded a valid USB reset 0 1 read-write KEEP_ALIVE_CTRL Keep Alive mode control 0x124 8 read-write n 0x0 0x0 KEEP_ALIVE_EN Global enable for USB_KEEP_ALIVE mode 0 1 read-write OWN_OVERRD_EN When set to 1, during KEEP_ALIVE mode, if received token is not SETUP, the OWN bit of current BD will be forced to 0, so usb core will respond with NAK 1 1 read-write WAKE_INT_EN Wakeup Interrupt Enable. 4 1 read-write WAKE_INT_STS Wakeup Interrupt Status. 7 1 read-only WAKE_REQ_EN During KEEP_ALIVE mode, a bus access by the USB controller to a memory location outside the USB SRAM will cause the bus access to stall until KEEP_ALIVE mode is exited 3 1 read-write 0 USB bus wakeup request is disabled. #0 1 USB bus wakeup request is enabled. #1 KEEP_ALIVE_WKCTRL Keep Alive mode wakeup control 0x128 8 read-write n 0x0 0x0 WAKE_ENDPT Indicates which endpoint causes the wakeup interrupt. Reset to 0, software read only. 4 4 read-only WAKE_ON_THIS Software configure it to which token can wakeup usb during KEEP_ALIVE mode 0 4 read-write 0001 Wake up on receiving OUT/SETUP token packet. #0001 1101 Wake up on receiving SETUP token packet.All other values are reserved. #1101 MISCCTRL Miscellaneous Control register 0x12C 8 read-write n 0x0 0x0 OWNERRISODIS OWN Error Detect for ISO IN / ISO OUT Disable 2 1 read-write 0 OWN error detect for ISO IN / ISO OUT is not disabled. #0 1 OWN error detect for ISO IN / ISO OUT is disabled. #1 SOFBUSSET SOF_TOK Interrupt Generation Mode Select 1 1 read-write 0 SOF_TOK interrupt is set according to SOF threshold value. #0 1 SOF_TOK interrupt is set when SOF counter reaches 0. #1 SOFDYNTHLD Dynamic SOF Threshold Compare mode 0 1 read-write 0 SOF_TOK interrupt is set when byte times SOF threshold is reached. #0 1 SOF_TOK interrupt is set when 8 byte times SOF threshold is reached or overstepped. #1 VFEDG_EN VREGIN Falling Edge Interrupt Enable 4 1 read-write 0 VREGIN falling edge interrupt disabled. #0 1 VREGIN falling edge interrupt enabled. #1 VREDG_EN VREGIN Rising Edge Interrupt Enable 3 1 read-write 0 VREGIN rising edge interrupt disabled. #0 1 VREGIN rising edge interrupt enabled. #1 OBSERVE USB OTG Observe register 0x104 8 read-only n 0x0 0x0 DMPD Provides observability of the D- Pulldown enable at the USB transceiver. 4 1 read-only 0 D- pulldown disabled. #0 1 D- pulldown enabled. #1 DPPD Provides observability of the D+ Pulldown enable at the USB transceiver. 6 1 read-only 0 D+ pulldown disabled. #0 1 D+ pulldown enabled. #1 DPPU Provides observability of the D+ Pullup enable at the USB transceiver. 7 1 read-only 0 D+ pullup disabled. #0 1 D+ pullup enabled. #1 OTGCTL OTG Control register 0x1C 8 read-write n 0x0 0x0 DMLOW D- Data Line pull-down resistor enable 4 1 read-write 0 D- pulldown resistor is not enabled. #0 1 D- pulldown resistor is enabled. #1 DPHIGH D+ Data Line pullup resistor enable 7 1 read-write 0 D+ pullup resistor is not enabled #0 1 D+ pullup resistor is enabled #1 DPLOW D+ Data Line pull-down resistor enable 5 1 read-write 0 D+ pulldown resistor is not enabled. #0 1 D+ pulldown resistor is enabled. #1 OTGEN On-The-Go pullup/pulldown resistor enable 2 1 read-write 0 If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then the D+ Data Line pull-up resistors are enabled. If HOST_MODE is 1 the D+ and D- Data Line pull-down resistors are engaged. #0 1 The pull-up and pull-down controls in this register are used. #1 OTGICR OTG Interrupt Control register 0x14 8 read-write n 0x0 0x0 LINESTATEEN Line State Change Interrupt Enable 5 1 read-write 0 Disables the LINE_STAT_CHG interrupt. #0 1 Enables the LINE_STAT_CHG interrupt. #1 ONEMSECEN One Millisecond Interrupt Enable 6 1 read-write 0 Diables the 1ms timer interrupt. #0 1 Enables the 1ms timer interrupt. #1 OTGISTAT OTG Interrupt Status register 0x10 8 read-write n 0x0 0x0 LINE_STATE_CHG This interrupt is set when the USB line state (CTL[SE0] and CTL[JSTATE] bits) are stable without change for 1 millisecond, and the value of the line state is different from the last time when the line state was stable 5 1 read-write ONEMSEC This bit is set when the 1 millisecond timer expires 6 1 read-write OTGSTAT OTG Status register 0x18 8 read-write n 0x0 0x0 LINESTATESTABLE Indicates that the internal signals that control the LINE_STATE_CHG field of OTGISTAT are stable for at least 1 ms 5 1 read-write 0 The LINE_STAT_CHG bit is not yet stable. #0 1 The LINE_STAT_CHG bit has been debounced and is stable. #1 ONEMSECEN This bit is reserved for the 1ms count, but it is not useful to software. 6 1 read-write PERID Peripheral ID register 0x0 8 read-only n 0x0 0x0 ID Peripheral Identification 0 6 read-only REV Peripheral Revision register 0x8 8 read-only n 0x0 0x0 REV Revision 0 8 read-only SOFTHLD SOF Threshold register 0xAC 8 read-write n 0x0 0x0 CNT Represents the SOF count threshold in byte times when SOFDYNTHLD=0 or 8 byte times when SOFDYNTHLD=1 0 8 read-write STAT Status register 0x90 8 read-only n 0x0 0x0 ENDP This four-bit field encodes the endpoint address that received or transmitted the previous token 4 4 read-only ODD This bit is set if the last buffer descriptor updated was in the odd bank of the BDT. 2 1 read-only TX Transmit Indicator 3 1 read-only 0 The most recent transaction was a receive operation. #0 1 The most recent transaction was a transmit operation. #1 TOKEN Token register 0xA8 8 read-write n 0x0 0x0 TOKENENDPT Holds the Endpoint address for the token command 0 4 read-write TOKENPID Contains the token type executed by the USB module. 4 4 read-write 0001 OUT Token. USB Module performs an OUT (TX) transaction. #0001 1001 IN Token. USB Module performs an In (RX) transaction. #1001 1101 SETUP Token. USB Module performs a SETUP (TX) transaction #1101 USBCTRL USB Control register 0x100 8 read-write n 0x0 0x0 PDE Enables the weak pulldowns on the USB transceiver. 6 1 read-write 0 Weak pulldowns are disabled on D+ and D-. #0 1 Weak pulldowns are enabled on D+ and D-. #1 SUSP Places the USB transceiver into the suspend state. 7 1 read-write 0 USB transceiver is not in suspend state. #0 1 USB transceiver is in suspend state. #1 UARTCHLS UART Signal Channel Select 5 1 read-write 0 USB DP/DM signals used as UART TX/RX. #0 1 USB DP/DM signals used as UART RX/TX. #1 UARTSEL Selects USB signals to be used as UART signals. 4 1 read-write 0 USB signals not used as UART signals. #0 1 USB signals used as UART signals. #1 USBFRMADJUST Frame Adjust Register 0x114 8 read-write n 0x0 0x0 ADJ Frame Adjustment 0 8 read-write USBTRC0 USB Transceiver Control register 0 0x10C 8 read-write n 0x0 0x0 SYNC_DET Synchronous USB Interrupt Detect 1 1 read-only 0 Synchronous interrupt has not been detected. #0 1 Synchronous interrupt has been detected. #1 USBRESET USB Reset 7 1 write-only 0 Normal USB module operation. #0 1 Returns the USB module to its reset state. #1 USBRESMEN Asynchronous Resume Interrupt Enable 5 1 read-write 0 USB asynchronous wakeup from suspend mode disabled. #0 1 USB asynchronous wakeup from suspend mode enabled. The asynchronous resume interrupt differs from the synchronous resume interrupt in that it asynchronously detects K-state using the unfiltered state of the D+ and D- pins. This interrupt should only be enabled when the Transceiver is suspended. #1 USB_CLK_RECOVERY_INT Combined USB Clock Recovery interrupt status 2 1 read-only USB_RESUME_INT USB Asynchronous Interrupt 0 1 read-only 0 No interrupt was generated. #0 1 Interrupt was generated because of the USB asynchronous interrupt. #1 VFEDG_DET VREGIN Falling Edge Interrupt Detect 4 1 read-only 0 VREGIN falling edge interrupt has not been detected. #0 1 VREGIN falling edge interrupt has been detected. #1 VREDG_DET VREGIN Rising Edge Interrupt Detect 3 1 read-only 0 VREGIN rising edge interrupt has not been detected. #0 1 VREGIN rising edge interrupt has been detected. #1 VREF Voltage Reference VREF 0x0 0x0 0x6 registers n SC VREF Status and Control Register 0x1 8 read-write n 0x0 0x0 ICOMPEN Second order curvature compensation enable 5 1 read-write 0 Disabled #0 1 Enabled #1 MODE_LV Buffer Mode selection 0 2 read-write 00 Bandgap on only, for stabilization and startup #00 01 High power buffer mode enabled #01 10 Low-power buffer mode enabled #10 REGEN Regulator enable 6 1 read-write 0 Internal 1.75 V regulator is disabled. #0 1 Internal 1.75 V regulator is enabled. #1 TMUXEN Test MUX enable 3 1 read-write 0 Disabled #0 1 Enabled #1 TRESEN Test second order curvature compensation enable 4 1 read-write 0 Disabled #0 1 Enabled #1 VREFEN Internal Voltage Reference enable 7 1 read-write 0 The module is disabled. #0 1 The module is enabled. #1 VREFST Internal Voltage Reference stable 2 1 read-only 0 The module is disabled or not stable. #0 1 The module is stable. #1 TRM VREF Trim Register 0x0 8 read-write n 0x0 0x0 CHOPEN Chop oscillator enable. When set, the internal chopping operation is enabled and the internal analog offset will be minimized. 6 1 read-write 0 Chop oscillator is disabled. #0 1 Chop oscillator is enabled. #1 FLIP Reverses the amplifier polarity 7 1 read-write TRIM Trim bits 0 6 read-write 000000 Min #0 111111 Max #111111 TRM4 VREF Trim Register 4 0x5 8 read-write n 0x0 0x0 VREF2V1_EN Internal Voltage Reference (2.1V) Enable 7 1 read-write 0 VREF 2.1V is disabled #0 1 VREF 2.1V is enabled #1 WDOG0 Watchdog timer WDOG 0x0 0x0 0x10 registers n WDOG0 44 CNT Watchdog Counter Register 0x4 32 read-write n 0x0 0x0 CNTHIGH High byte of the Watchdog Counter 8 8 read-write CNTLOW Low byte of the Watchdog Counter 0 8 read-write CS Watchdog Control and Status Register 0x0 32 read-write n 0x0 0x0 CLK Watchdog Clock 8 2 read-write 00 Bus clock. #00 01 Internal low-power oscillator (LPOCLK). #01 10 8 MHz internal reference clock. #10 11 External clock source. #11 CMD32EN Enables or disables WDOG support for 32-bit (or 16-bit or 8-bit) refresh/unlock command write words 13 1 read-write 0 Disables support for 32-bit (or 16-bit or 8-bit) refresh/unlock command write words #0 1 Enables support for 32-bit (or 16-bit or 8-bit) refresh/unlock command write words #1 DBG Debug Enable 2 1 read-write 0 Watchdog disabled in chip debug mode. #0 1 Watchdog enabled in chip debug mode. #1 EN Watchdog Enable 7 1 read-write 0 Watchdog disabled. #0 1 Watchdog enabled. #1 FLG Watchdog Interrupt Flag 14 1 read-write 0 No interrupt occurred. #0 1 An interrupt occurred. #1 INT Watchdog Interrupt 6 1 read-write 0 Watchdog interrupts are disabled. Watchdog resets are not delayed. #0 1 Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch. #1 PRES Watchdog Prescalar 12 1 read-write 0 256 prescalar disabled. #0 1 256 prescalar enabled. #1 STOP Stop Enable 0 1 read-write 0 Watchdog disabled in chip stop mode. #0 1 Watchdog enabled in chip stop mode. #1 TST Watchdog Test 3 2 read-write 00 Watchdog test mode disabled. #00 01 Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode. #01 10 Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. #10 11 Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH]. #11 UPDATE Allow updates 5 1 read-write 0 Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. #0 1 Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. #1 WAIT Wait Enable 1 1 read-write 0 Watchdog disabled in chip wait mode. #0 1 Watchdog enabled in chip wait mode. #1 WIN Watchdog Window 15 1 read-write 0 Window mode disabled. #0 1 Window mode enabled. #1 TOVAL Watchdog Timeout Value Register 0x8 32 read-write n 0x0 0x0 TOVALHIGH High byte of the timeout value; 8 8 read-write TOVALLOW Low byte of the timeout value 0 8 read-write WIN Watchdog Window Register 0xC 32 read-write n 0x0 0x0 WINHIGH High byte of Watchdog Window 8 8 read-write WINLOW Low byte of Watchdog Window 0 8 read-write WDOG1 Watchdog timer WDOG 0x0 0x0 0x10 registers n CNT Watchdog Counter Register 0x4 32 read-write n 0x0 0x0 CNTHIGH High byte of the Watchdog Counter 8 8 read-write CNTLOW Low byte of the Watchdog Counter 0 8 read-write CS Watchdog Control and Status Register 0x0 32 read-write n 0x0 0x0 CLK Watchdog Clock 8 2 read-write 00 Bus clock. #00 01 Internal low-power oscillator (LPOCLK). #01 10 8 MHz internal reference clock. #10 11 External clock source. #11 CMD32EN Enables or disables WDOG support for 32-bit (or 16-bit or 8-bit) refresh/unlock command write words 13 1 read-write 0 Disables support for 32-bit (or 16-bit or 8-bit) refresh/unlock command write words #0 1 Enables support for 32-bit (or 16-bit or 8-bit) refresh/unlock command write words #1 DBG Debug Enable 2 1 read-write 0 Watchdog disabled in chip debug mode. #0 1 Watchdog enabled in chip debug mode. #1 EN Watchdog Enable 7 1 read-write 0 Watchdog disabled. #0 1 Watchdog enabled. #1 FLG Watchdog Interrupt Flag 14 1 read-write 0 No interrupt occurred. #0 1 An interrupt occurred. #1 INT Watchdog Interrupt 6 1 read-write 0 Watchdog interrupts are disabled. Watchdog resets are not delayed. #0 1 Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch. #1 PRES Watchdog Prescalar 12 1 read-write 0 256 prescalar disabled. #0 1 256 prescalar enabled. #1 STOP Stop Enable 0 1 read-write 0 Watchdog disabled in chip stop mode. #0 1 Watchdog enabled in chip stop mode. #1 TST Watchdog Test 3 2 read-write 00 Watchdog test mode disabled. #00 01 Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode. #01 10 Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. #10 11 Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH]. #11 UPDATE Allow updates 5 1 read-write 0 Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. #0 1 Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. #1 WAIT Wait Enable 1 1 read-write 0 Watchdog disabled in chip wait mode. #0 1 Watchdog enabled in chip wait mode. #1 WIN Watchdog Window 15 1 read-write 0 Window mode disabled. #0 1 Window mode enabled. #1 TOVAL Watchdog Timeout Value Register 0x8 32 read-write n 0x0 0x0 TOVALHIGH High byte of the timeout value; 8 8 read-write TOVALLOW Low byte of the timeout value 0 8 read-write WIN Watchdog Window Register 0xC 32 read-write n 0x0 0x0 WINHIGH High byte of Watchdog Window 8 8 read-write WINLOW Low byte of Watchdog Window 0 8 read-write XRDC XRDC XRDC 0x0 0x0 0x2300 registers n CR Control Register 0x0 32 read-write n 0x0 0x0 GVLD Global Valid (XRDC global enable/disable). 0 1 read-write 0 XRDC is disabled. All accesses from all bus masters to all slaves are allowed. #0 1 XRDC is enabled. #1 HRL Hardware Revision Level 1 4 read-only LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 MRF Memory Region Format 7 1 read-only 0 Kinetis format based on ARM Cortex-M processor core definition. #0 VAW Virtualization aware 8 1 read-only 0 Implementation is not virtualization aware. #0 1 Implementation is virtualization aware. #1 DERRLOC0 Domain Error Location Register 0x400 32 read-only n 0x0 0x0 MRCINST MRC instance 0 16 read-only 0 The MRC has not detected an access violation or is not physically present. #0 1 The MRC has detected one or more access violations for this domain. #1 PACINST PAC instance 16 4 read-only 0 The PAC has not detected an access violation or is not physically present. #0000 1 The PAC has detected one or more access violations for this domain. #0001 DERRLOC1 Domain Error Location Register 0x604 32 read-only n 0x0 0x0 MRCINST MRC instance 0 16 read-only 0 The MRC has not detected an access violation or is not physically present. #0 1 The MRC has detected one or more access violations for this domain. #1 PACINST PAC instance 16 4 read-only 0 The PAC has not detected an access violation or is not physically present. #0000 1 The PAC has detected one or more access violations for this domain. #0001 DERRLOC2 Domain Error Location Register 0x80C 32 read-only n 0x0 0x0 MRCINST MRC instance 0 16 read-only 0 The MRC has not detected an access violation or is not physically present. #0 1 The MRC has detected one or more access violations for this domain. #1 PACINST PAC instance 16 4 read-only 0 The PAC has not detected an access violation or is not physically present. #0000 1 The PAC has detected one or more access violations for this domain. #0001 DERR_W0_0 Domain Error Word0 Register 0x800 32 read-only n 0x0 0x0 EADDR Error address. This is the access address that generated an access violation. 0 32 read-only DERR_W0_1 Domain Error Word0 Register 0xC10 32 read-only n 0x0 0x0 EADDR Error address. This is the access address that generated an access violation. 0 32 read-only DERR_W0_10 Domain Error Word0 Register 0x3370 32 read-only n 0x0 0x0 EADDR Error address. This is the access address that generated an access violation. 0 32 read-only DERR_W0_11 Domain Error Word0 Register 0x3820 32 read-only n 0x0 0x0 EADDR Error address. This is the access address that generated an access violation. 0 32 read-only DERR_W0_12 Domain Error Word0 Register 0x3CE0 32 read-only n 0x0 0x0 EADDR Error address. This is the access address that generated an access violation. 0 32 read-only DERR_W0_13 Domain Error Word0 Register 0x41B0 32 read-only n 0x0 0x0 EADDR Error address. This is the access address that generated an access violation. 0 32 read-only DERR_W0_14 Domain Error Word0 Register 0x4690 32 read-only n 0x0 0x0 EADDR Error address. This is the access address that generated an access violation. 0 32 read-only DERR_W0_15 Domain Error Word0 Register 0x4B80 32 read-only n 0x0 0x0 EADDR Error address. This is the access address that generated an access violation. 0 32 read-only DERR_W0_16 Domain Error Word0 Register 0x5080 32 read-only n 0x0 0x0 EADDR Error address. This is the access address that generated an access violation. 0 32 read-only DERR_W0_17 Domain Error Word0 Register 0x5590 32 read-only n 0x0 0x0 EADDR Error address. This is the access address that generated an access violation. 0 32 read-only DERR_W0_18 Domain Error Word0 Register 0x5AB0 32 read-only n 0x0 0x0 EADDR Error address. This is the access address that generated an access violation. 0 32 read-only DERR_W0_2 Domain Error Word0 Register 0x1030 32 read-only n 0x0 0x0 EADDR Error address. This is the access address that generated an access violation. 0 32 read-only DERR_W0_3 Domain Error Word0 Register 0x1460 32 read-only n 0x0 0x0 EADDR Error address. This is the access address that generated an access violation. 0 32 read-only DERR_W0_4 Domain Error Word0 Register 0x18A0 32 read-only n 0x0 0x0 EADDR Error address. This is the access address that generated an access violation. 0 32 read-only DERR_W0_5 Domain Error Word0 Register 0x1CF0 32 read-only n 0x0 0x0 EADDR Error address. This is the access address that generated an access violation. 0 32 read-only DERR_W0_6 Domain Error Word0 Register 0x2150 32 read-only n 0x0 0x0 EADDR Error address. This is the access address that generated an access violation. 0 32 read-only DERR_W0_7 Domain Error Word0 Register 0x25C0 32 read-only n 0x0 0x0 EADDR Error address. This is the access address that generated an access violation. 0 32 read-only DERR_W0_8 Domain Error Word0 Register 0x2A40 32 read-only n 0x0 0x0 EADDR Error address. This is the access address that generated an access violation. 0 32 read-only DERR_W0_9 Domain Error Word0 Register 0x2ED0 32 read-only n 0x0 0x0 EADDR Error address. This is the access address that generated an access violation. 0 32 read-only DERR_W1_0 Domain Error Word1 Register 0x808 32 read-only n 0x0 0x0 EATR Error attributes. This field captures certain attributes of the access violation. 8 3 read-only 000 Secure user mode, instruction fetch access #000 001 Secure user mode, data access #001 010 Secure privileged mode, instruction fetch access #010 011 Secure privileged mode, data access #011 100 Nonsecure user mode, instruction fetch access #100 101 Nonsecure user mode, data access #101 110 Nonsecure privileged mode, instruction fetch access #110 111 Nonsecure privileged mode, data access #111 EDID Error domain identifier. This field captures the domain identifier of the access violation. 0 4 read-only EPORT Error port 24 3 read-only ERW Error read/write 11 1 read-only 0 Read access #0 1 Write access #1 EST Error state 30 2 read-only 00 No access violation has been detected. #00 01 No access violation has been detected. #01 10 A single access violation has been detected. #10 11 Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_n and DERR_W1_n. #11 DERR_W1_1 Domain Error Word1 Register 0xC1C 32 read-only n 0x0 0x0 EATR Error attributes. This field captures certain attributes of the access violation. 8 3 read-only 000 Secure user mode, instruction fetch access #000 001 Secure user mode, data access #001 010 Secure privileged mode, instruction fetch access #010 011 Secure privileged mode, data access #011 100 Nonsecure user mode, instruction fetch access #100 101 Nonsecure user mode, data access #101 110 Nonsecure privileged mode, instruction fetch access #110 111 Nonsecure privileged mode, data access #111 EDID Error domain identifier. This field captures the domain identifier of the access violation. 0 4 read-only EPORT Error port 24 3 read-only ERW Error read/write 11 1 read-only 0 Read access #0 1 Write access #1 EST Error state 30 2 read-only 00 No access violation has been detected. #00 01 No access violation has been detected. #01 10 A single access violation has been detected. #10 11 Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_n and DERR_W1_n. #11 DERR_W1_10 Domain Error Word1 Register 0x33A0 32 read-only n 0x0 0x0 EATR Error attributes. This field captures certain attributes of the access violation. 8 3 read-only 000 Secure user mode, instruction fetch access #000 001 Secure user mode, data access #001 010 Secure privileged mode, instruction fetch access #010 011 Secure privileged mode, data access #011 100 Nonsecure user mode, instruction fetch access #100 101 Nonsecure user mode, data access #101 110 Nonsecure privileged mode, instruction fetch access #110 111 Nonsecure privileged mode, data access #111 EDID Error domain identifier. This field captures the domain identifier of the access violation. 0 4 read-only EPORT Error port 24 3 read-only ERW Error read/write 11 1 read-only 0 Read access #0 1 Write access #1 EST Error state 30 2 read-only 00 No access violation has been detected. #00 01 No access violation has been detected. #01 10 A single access violation has been detected. #10 11 Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_n and DERR_W1_n. #11 DERR_W1_11 Domain Error Word1 Register 0x3854 32 read-only n 0x0 0x0 EATR Error attributes. This field captures certain attributes of the access violation. 8 3 read-only 000 Secure user mode, instruction fetch access #000 001 Secure user mode, data access #001 010 Secure privileged mode, instruction fetch access #010 011 Secure privileged mode, data access #011 100 Nonsecure user mode, instruction fetch access #100 101 Nonsecure user mode, data access #101 110 Nonsecure privileged mode, instruction fetch access #110 111 Nonsecure privileged mode, data access #111 EDID Error domain identifier. This field captures the domain identifier of the access violation. 0 4 read-only EPORT Error port 24 3 read-only ERW Error read/write 11 1 read-only 0 Read access #0 1 Write access #1 EST Error state 30 2 read-only 00 No access violation has been detected. #00 01 No access violation has been detected. #01 10 A single access violation has been detected. #10 11 Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_n and DERR_W1_n. #11 DERR_W1_12 Domain Error Word1 Register 0x3D18 32 read-only n 0x0 0x0 EATR Error attributes. This field captures certain attributes of the access violation. 8 3 read-only 000 Secure user mode, instruction fetch access #000 001 Secure user mode, data access #001 010 Secure privileged mode, instruction fetch access #010 011 Secure privileged mode, data access #011 100 Nonsecure user mode, instruction fetch access #100 101 Nonsecure user mode, data access #101 110 Nonsecure privileged mode, instruction fetch access #110 111 Nonsecure privileged mode, data access #111 EDID Error domain identifier. This field captures the domain identifier of the access violation. 0 4 read-only EPORT Error port 24 3 read-only ERW Error read/write 11 1 read-only 0 Read access #0 1 Write access #1 EST Error state 30 2 read-only 00 No access violation has been detected. #00 01 No access violation has been detected. #01 10 A single access violation has been detected. #10 11 Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_n and DERR_W1_n. #11 DERR_W1_13 Domain Error Word1 Register 0x41EC 32 read-only n 0x0 0x0 EATR Error attributes. This field captures certain attributes of the access violation. 8 3 read-only 000 Secure user mode, instruction fetch access #000 001 Secure user mode, data access #001 010 Secure privileged mode, instruction fetch access #010 011 Secure privileged mode, data access #011 100 Nonsecure user mode, instruction fetch access #100 101 Nonsecure user mode, data access #101 110 Nonsecure privileged mode, instruction fetch access #110 111 Nonsecure privileged mode, data access #111 EDID Error domain identifier. This field captures the domain identifier of the access violation. 0 4 read-only EPORT Error port 24 3 read-only ERW Error read/write 11 1 read-only 0 Read access #0 1 Write access #1 EST Error state 30 2 read-only 00 No access violation has been detected. #00 01 No access violation has been detected. #01 10 A single access violation has been detected. #10 11 Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_n and DERR_W1_n. #11 DERR_W1_14 Domain Error Word1 Register 0x46D0 32 read-only n 0x0 0x0 EATR Error attributes. This field captures certain attributes of the access violation. 8 3 read-only 000 Secure user mode, instruction fetch access #000 001 Secure user mode, data access #001 010 Secure privileged mode, instruction fetch access #010 011 Secure privileged mode, data access #011 100 Nonsecure user mode, instruction fetch access #100 101 Nonsecure user mode, data access #101 110 Nonsecure privileged mode, instruction fetch access #110 111 Nonsecure privileged mode, data access #111 EDID Error domain identifier. This field captures the domain identifier of the access violation. 0 4 read-only EPORT Error port 24 3 read-only ERW Error read/write 11 1 read-only 0 Read access #0 1 Write access #1 EST Error state 30 2 read-only 00 No access violation has been detected. #00 01 No access violation has been detected. #01 10 A single access violation has been detected. #10 11 Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_n and DERR_W1_n. #11 DERR_W1_15 Domain Error Word1 Register 0x4BC4 32 read-only n 0x0 0x0 EATR Error attributes. This field captures certain attributes of the access violation. 8 3 read-only 000 Secure user mode, instruction fetch access #000 001 Secure user mode, data access #001 010 Secure privileged mode, instruction fetch access #010 011 Secure privileged mode, data access #011 100 Nonsecure user mode, instruction fetch access #100 101 Nonsecure user mode, data access #101 110 Nonsecure privileged mode, instruction fetch access #110 111 Nonsecure privileged mode, data access #111 EDID Error domain identifier. This field captures the domain identifier of the access violation. 0 4 read-only EPORT Error port 24 3 read-only ERW Error read/write 11 1 read-only 0 Read access #0 1 Write access #1 EST Error state 30 2 read-only 00 No access violation has been detected. #00 01 No access violation has been detected. #01 10 A single access violation has been detected. #10 11 Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_n and DERR_W1_n. #11 DERR_W1_16 Domain Error Word1 Register 0x50C8 32 read-only n 0x0 0x0 EATR Error attributes. This field captures certain attributes of the access violation. 8 3 read-only 000 Secure user mode, instruction fetch access #000 001 Secure user mode, data access #001 010 Secure privileged mode, instruction fetch access #010 011 Secure privileged mode, data access #011 100 Nonsecure user mode, instruction fetch access #100 101 Nonsecure user mode, data access #101 110 Nonsecure privileged mode, instruction fetch access #110 111 Nonsecure privileged mode, data access #111 EDID Error domain identifier. This field captures the domain identifier of the access violation. 0 4 read-only EPORT Error port 24 3 read-only ERW Error read/write 11 1 read-only 0 Read access #0 1 Write access #1 EST Error state 30 2 read-only 00 No access violation has been detected. #00 01 No access violation has been detected. #01 10 A single access violation has been detected. #10 11 Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_n and DERR_W1_n. #11 DERR_W1_17 Domain Error Word1 Register 0x55DC 32 read-only n 0x0 0x0 EATR Error attributes. This field captures certain attributes of the access violation. 8 3 read-only 000 Secure user mode, instruction fetch access #000 001 Secure user mode, data access #001 010 Secure privileged mode, instruction fetch access #010 011 Secure privileged mode, data access #011 100 Nonsecure user mode, instruction fetch access #100 101 Nonsecure user mode, data access #101 110 Nonsecure privileged mode, instruction fetch access #110 111 Nonsecure privileged mode, data access #111 EDID Error domain identifier. This field captures the domain identifier of the access violation. 0 4 read-only EPORT Error port 24 3 read-only ERW Error read/write 11 1 read-only 0 Read access #0 1 Write access #1 EST Error state 30 2 read-only 00 No access violation has been detected. #00 01 No access violation has been detected. #01 10 A single access violation has been detected. #10 11 Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_n and DERR_W1_n. #11 DERR_W1_18 Domain Error Word1 Register 0x5B00 32 read-only n 0x0 0x0 EATR Error attributes. This field captures certain attributes of the access violation. 8 3 read-only 000 Secure user mode, instruction fetch access #000 001 Secure user mode, data access #001 010 Secure privileged mode, instruction fetch access #010 011 Secure privileged mode, data access #011 100 Nonsecure user mode, instruction fetch access #100 101 Nonsecure user mode, data access #101 110 Nonsecure privileged mode, instruction fetch access #110 111 Nonsecure privileged mode, data access #111 EDID Error domain identifier. This field captures the domain identifier of the access violation. 0 4 read-only EPORT Error port 24 3 read-only ERW Error read/write 11 1 read-only 0 Read access #0 1 Write access #1 EST Error state 30 2 read-only 00 No access violation has been detected. #00 01 No access violation has been detected. #01 10 A single access violation has been detected. #10 11 Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_n and DERR_W1_n. #11 DERR_W1_2 Domain Error Word1 Register 0x1040 32 read-only n 0x0 0x0 EATR Error attributes. This field captures certain attributes of the access violation. 8 3 read-only 000 Secure user mode, instruction fetch access #000 001 Secure user mode, data access #001 010 Secure privileged mode, instruction fetch access #010 011 Secure privileged mode, data access #011 100 Nonsecure user mode, instruction fetch access #100 101 Nonsecure user mode, data access #101 110 Nonsecure privileged mode, instruction fetch access #110 111 Nonsecure privileged mode, data access #111 EDID Error domain identifier. This field captures the domain identifier of the access violation. 0 4 read-only EPORT Error port 24 3 read-only ERW Error read/write 11 1 read-only 0 Read access #0 1 Write access #1 EST Error state 30 2 read-only 00 No access violation has been detected. #00 01 No access violation has been detected. #01 10 A single access violation has been detected. #10 11 Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_n and DERR_W1_n. #11 DERR_W1_3 Domain Error Word1 Register 0x1474 32 read-only n 0x0 0x0 EATR Error attributes. This field captures certain attributes of the access violation. 8 3 read-only 000 Secure user mode, instruction fetch access #000 001 Secure user mode, data access #001 010 Secure privileged mode, instruction fetch access #010 011 Secure privileged mode, data access #011 100 Nonsecure user mode, instruction fetch access #100 101 Nonsecure user mode, data access #101 110 Nonsecure privileged mode, instruction fetch access #110 111 Nonsecure privileged mode, data access #111 EDID Error domain identifier. This field captures the domain identifier of the access violation. 0 4 read-only EPORT Error port 24 3 read-only ERW Error read/write 11 1 read-only 0 Read access #0 1 Write access #1 EST Error state 30 2 read-only 00 No access violation has been detected. #00 01 No access violation has been detected. #01 10 A single access violation has been detected. #10 11 Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_n and DERR_W1_n. #11 DERR_W1_4 Domain Error Word1 Register 0x18B8 32 read-only n 0x0 0x0 EATR Error attributes. This field captures certain attributes of the access violation. 8 3 read-only 000 Secure user mode, instruction fetch access #000 001 Secure user mode, data access #001 010 Secure privileged mode, instruction fetch access #010 011 Secure privileged mode, data access #011 100 Nonsecure user mode, instruction fetch access #100 101 Nonsecure user mode, data access #101 110 Nonsecure privileged mode, instruction fetch access #110 111 Nonsecure privileged mode, data access #111 EDID Error domain identifier. This field captures the domain identifier of the access violation. 0 4 read-only EPORT Error port 24 3 read-only ERW Error read/write 11 1 read-only 0 Read access #0 1 Write access #1 EST Error state 30 2 read-only 00 No access violation has been detected. #00 01 No access violation has been detected. #01 10 A single access violation has been detected. #10 11 Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_n and DERR_W1_n. #11 DERR_W1_5 Domain Error Word1 Register 0x1D0C 32 read-only n 0x0 0x0 EATR Error attributes. This field captures certain attributes of the access violation. 8 3 read-only 000 Secure user mode, instruction fetch access #000 001 Secure user mode, data access #001 010 Secure privileged mode, instruction fetch access #010 011 Secure privileged mode, data access #011 100 Nonsecure user mode, instruction fetch access #100 101 Nonsecure user mode, data access #101 110 Nonsecure privileged mode, instruction fetch access #110 111 Nonsecure privileged mode, data access #111 EDID Error domain identifier. This field captures the domain identifier of the access violation. 0 4 read-only EPORT Error port 24 3 read-only ERW Error read/write 11 1 read-only 0 Read access #0 1 Write access #1 EST Error state 30 2 read-only 00 No access violation has been detected. #00 01 No access violation has been detected. #01 10 A single access violation has been detected. #10 11 Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_n and DERR_W1_n. #11 DERR_W1_6 Domain Error Word1 Register 0x2170 32 read-only n 0x0 0x0 EATR Error attributes. This field captures certain attributes of the access violation. 8 3 read-only 000 Secure user mode, instruction fetch access #000 001 Secure user mode, data access #001 010 Secure privileged mode, instruction fetch access #010 011 Secure privileged mode, data access #011 100 Nonsecure user mode, instruction fetch access #100 101 Nonsecure user mode, data access #101 110 Nonsecure privileged mode, instruction fetch access #110 111 Nonsecure privileged mode, data access #111 EDID Error domain identifier. This field captures the domain identifier of the access violation. 0 4 read-only EPORT Error port 24 3 read-only ERW Error read/write 11 1 read-only 0 Read access #0 1 Write access #1 EST Error state 30 2 read-only 00 No access violation has been detected. #00 01 No access violation has been detected. #01 10 A single access violation has been detected. #10 11 Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_n and DERR_W1_n. #11 DERR_W1_7 Domain Error Word1 Register 0x25E4 32 read-only n 0x0 0x0 EATR Error attributes. This field captures certain attributes of the access violation. 8 3 read-only 000 Secure user mode, instruction fetch access #000 001 Secure user mode, data access #001 010 Secure privileged mode, instruction fetch access #010 011 Secure privileged mode, data access #011 100 Nonsecure user mode, instruction fetch access #100 101 Nonsecure user mode, data access #101 110 Nonsecure privileged mode, instruction fetch access #110 111 Nonsecure privileged mode, data access #111 EDID Error domain identifier. This field captures the domain identifier of the access violation. 0 4 read-only EPORT Error port 24 3 read-only ERW Error read/write 11 1 read-only 0 Read access #0 1 Write access #1 EST Error state 30 2 read-only 00 No access violation has been detected. #00 01 No access violation has been detected. #01 10 A single access violation has been detected. #10 11 Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_n and DERR_W1_n. #11 DERR_W1_8 Domain Error Word1 Register 0x2A68 32 read-only n 0x0 0x0 EATR Error attributes. This field captures certain attributes of the access violation. 8 3 read-only 000 Secure user mode, instruction fetch access #000 001 Secure user mode, data access #001 010 Secure privileged mode, instruction fetch access #010 011 Secure privileged mode, data access #011 100 Nonsecure user mode, instruction fetch access #100 101 Nonsecure user mode, data access #101 110 Nonsecure privileged mode, instruction fetch access #110 111 Nonsecure privileged mode, data access #111 EDID Error domain identifier. This field captures the domain identifier of the access violation. 0 4 read-only EPORT Error port 24 3 read-only ERW Error read/write 11 1 read-only 0 Read access #0 1 Write access #1 EST Error state 30 2 read-only 00 No access violation has been detected. #00 01 No access violation has been detected. #01 10 A single access violation has been detected. #10 11 Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_n and DERR_W1_n. #11 DERR_W1_9 Domain Error Word1 Register 0x2EFC 32 read-only n 0x0 0x0 EATR Error attributes. This field captures certain attributes of the access violation. 8 3 read-only 000 Secure user mode, instruction fetch access #000 001 Secure user mode, data access #001 010 Secure privileged mode, instruction fetch access #010 011 Secure privileged mode, data access #011 100 Nonsecure user mode, instruction fetch access #100 101 Nonsecure user mode, data access #101 110 Nonsecure privileged mode, instruction fetch access #110 111 Nonsecure privileged mode, data access #111 EDID Error domain identifier. This field captures the domain identifier of the access violation. 0 4 read-only EPORT Error port 24 3 read-only ERW Error read/write 11 1 read-only 0 Read access #0 1 Write access #1 EST Error state 30 2 read-only 00 No access violation has been detected. #00 01 No access violation has been detected. #01 10 A single access violation has been detected. #10 11 Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_n and DERR_W1_n. #11 DERR_W2_0 Domain Error Word2 Register 0x810 32 read-only n 0x0 0x0 DERR_W2_1 Domain Error Word2 Register 0xC28 32 read-only n 0x0 0x0 DERR_W2_10 Domain Error Word2 Register 0x33D0 32 read-only n 0x0 0x0 DERR_W2_11 Domain Error Word2 Register 0x3888 32 read-only n 0x0 0x0 DERR_W2_12 Domain Error Word2 Register 0x3D50 32 read-only n 0x0 0x0 DERR_W2_13 Domain Error Word2 Register 0x4228 32 read-only n 0x0 0x0 DERR_W2_14 Domain Error Word2 Register 0x4710 32 read-only n 0x0 0x0 DERR_W2_15 Domain Error Word2 Register 0x4C08 32 read-only n 0x0 0x0 DERR_W2_16 Domain Error Word2 Register 0x5110 32 read-only n 0x0 0x0 DERR_W2_17 Domain Error Word2 Register 0x5628 32 read-only n 0x0 0x0 DERR_W2_18 Domain Error Word2 Register 0x5B50 32 read-only n 0x0 0x0 DERR_W2_2 Domain Error Word2 Register 0x1050 32 read-only n 0x0 0x0 DERR_W2_3 Domain Error Word2 Register 0x1488 32 read-only n 0x0 0x0 DERR_W2_4 Domain Error Word2 Register 0x18D0 32 read-only n 0x0 0x0 DERR_W2_5 Domain Error Word2 Register 0x1D28 32 read-only n 0x0 0x0 DERR_W2_6 Domain Error Word2 Register 0x2190 32 read-only n 0x0 0x0 DERR_W2_7 Domain Error Word2 Register 0x2608 32 read-only n 0x0 0x0 DERR_W2_8 Domain Error Word2 Register 0x2A90 32 read-only n 0x0 0x0 DERR_W2_9 Domain Error Word2 Register 0x2F28 32 read-only n 0x0 0x0 DERR_W3_0 Domain Error Word3 Register 0x818 32 read-write n 0x0 0x0 RECR Rearm Error Capture Registers 30 2 write-only DERR_W3_1 Domain Error Word3 Register 0xC34 32 read-write n 0x0 0x0 RECR Rearm Error Capture Registers 30 2 write-only DERR_W3_10 Domain Error Word3 Register 0x3400 32 read-write n 0x0 0x0 RECR Rearm Error Capture Registers 30 2 write-only DERR_W3_11 Domain Error Word3 Register 0x38BC 32 read-write n 0x0 0x0 RECR Rearm Error Capture Registers 30 2 write-only DERR_W3_12 Domain Error Word3 Register 0x3D88 32 read-write n 0x0 0x0 RECR Rearm Error Capture Registers 30 2 write-only DERR_W3_13 Domain Error Word3 Register 0x4264 32 read-write n 0x0 0x0 RECR Rearm Error Capture Registers 30 2 write-only DERR_W3_14 Domain Error Word3 Register 0x4750 32 read-write n 0x0 0x0 RECR Rearm Error Capture Registers 30 2 write-only DERR_W3_15 Domain Error Word3 Register 0x4C4C 32 read-write n 0x0 0x0 RECR Rearm Error Capture Registers 30 2 write-only DERR_W3_16 Domain Error Word3 Register 0x5158 32 read-write n 0x0 0x0 RECR Rearm Error Capture Registers 30 2 write-only DERR_W3_17 Domain Error Word3 Register 0x5674 32 read-write n 0x0 0x0 RECR Rearm Error Capture Registers 30 2 write-only DERR_W3_18 Domain Error Word3 Register 0x5BA0 32 read-write n 0x0 0x0 RECR Rearm Error Capture Registers 30 2 write-only DERR_W3_2 Domain Error Word3 Register 0x1060 32 read-write n 0x0 0x0 RECR Rearm Error Capture Registers 30 2 write-only DERR_W3_3 Domain Error Word3 Register 0x149C 32 read-write n 0x0 0x0 RECR Rearm Error Capture Registers 30 2 write-only DERR_W3_4 Domain Error Word3 Register 0x18E8 32 read-write n 0x0 0x0 RECR Rearm Error Capture Registers 30 2 write-only DERR_W3_5 Domain Error Word3 Register 0x1D44 32 read-write n 0x0 0x0 RECR Rearm Error Capture Registers 30 2 write-only DERR_W3_6 Domain Error Word3 Register 0x21B0 32 read-write n 0x0 0x0 RECR Rearm Error Capture Registers 30 2 write-only DERR_W3_7 Domain Error Word3 Register 0x262C 32 read-write n 0x0 0x0 RECR Rearm Error Capture Registers 30 2 write-only DERR_W3_8 Domain Error Word3 Register 0x2AB8 32 read-write n 0x0 0x0 RECR Rearm Error Capture Registers 30 2 write-only DERR_W3_9 Domain Error Word3 Register 0x2F54 32 read-write n 0x0 0x0 RECR Rearm Error Capture Registers 30 2 write-only HWCFG0 Hardware Configuration Register 0 0xF0 32 read-only n 0x0 0x0 NDID Number of domains 0 8 read-only NMRC Number of MRCs 16 8 read-only NMSTR Number of bus masters 8 8 read-only NPAC Number of PACs 24 4 read-only HWCFG1 Hardware Configuration Register 1 0xF4 32 read-only n 0x0 0x0 DID Domain identifier number 0 4 read-only HWCFG2 Hardware Configuration Register 2 0xF8 32 read-only n 0x0 0x0 PIDP0 Process identifier present from bus master 0 0 1 read-only 0 Bus master 0 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 0 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP1 Process identifier present from bus master 1 1 1 read-only 0 Bus master 1 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 1 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP10 Process identifier present from bus master 10 10 1 read-only 0 Bus master 10 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 10 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP11 Process identifier present from bus master 11 11 1 read-only 0 Bus master 11 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 11 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP12 Process identifier present from bus master 12 12 1 read-only 0 Bus master 12 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 12 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP13 Process identifier present from bus master 13 13 1 read-only 0 Bus master 13 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 13 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP14 Process identifier present from bus master 14 14 1 read-only 0 Bus master 14 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 14 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP15 Process identifier present from bus master 15 15 1 read-only 0 Bus master 15 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 15 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP16 Process identifier present from bus master 16 16 1 read-only 0 Bus master 16 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 16 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP17 Process identifier present from bus master 17 17 1 read-only 0 Bus master 17 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 17 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP18 Process identifier present from bus master 18 18 1 read-only 0 Bus master 18 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 18 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP19 Process identifier present from bus master 19 19 1 read-only 0 Bus master 19 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 19 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP2 Process identifier present from bus master 2 2 1 read-only 0 Bus master 2 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 2 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP20 Process identifier present from bus master 20 20 1 read-only 0 Bus master 20 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 20 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP21 Process identifier present from bus master 21 21 1 read-only 0 Bus master 21 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 21 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP22 Process identifier present from bus master 22 22 1 read-only 0 Bus master 22 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 22 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP23 Process identifier present from bus master 23 23 1 read-only 0 Bus master 23 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 23 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP24 Process identifier present from bus master 24 24 1 read-only 0 Bus master 24 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 24 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP25 Process identifier present from bus master 25 25 1 read-only 0 Bus master 25 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 25 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP26 Process identifier present from bus master 26 26 1 read-only 0 Bus master 26 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 26 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP27 Process identifier present from bus master 27 27 1 read-only 0 Bus master 27 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 27 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP28 Process identifier present from bus master 28 28 1 read-only 0 Bus master 28 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 28 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP29 Process identifier present from bus master 29 29 1 read-only 0 Bus master 29 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 29 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP3 Process identifier present from bus master 3 3 1 read-only 0 Bus master 3 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 3 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP30 Process identifier present from bus master 30 30 1 read-only 0 Bus master 30 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 30 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP31 Process identifier present from bus master 31 31 1 read-only 0 Bus master 31 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 31 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP4 Process identifier present from bus master 4 4 1 read-only 0 Bus master 4 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 4 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP5 Process identifier present from bus master 5 5 1 read-only 0 Bus master 5 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 5 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP6 Process identifier present from bus master 6 6 1 read-only 0 Bus master 6 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 6 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP7 Process identifier present from bus master 7 7 1 read-only 0 Bus master 7 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 7 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP8 Process identifier present from bus master 8 8 1 read-only 0 Bus master 8 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 8 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP9 Process identifier present from bus master 9 9 1 read-only 0 Bus master 9 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 9 sources a process identifier register to the XRDC_MDAC logic. #1 HWCFG3 Hardware Configuration Register 3 0xFC 32 read-only n 0x0 0x0 PIDP32 Process identifier present from bus master 32 0 1 read-only 0 Bus master 32 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 32 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP33 Process identifier present from bus master 33 1 1 read-only 0 Bus master 33 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 33 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP34 Process identifier present from bus master 34 2 1 read-only 0 Bus master 34 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 34 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP35 Process identifier present from bus master 35 3 1 read-only 0 Bus master 35 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 35 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP36 Process identifier present from bus master 36 4 1 read-only 0 Bus master 36 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 36 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP37 Process identifier present from bus master 37 5 1 read-only 0 Bus master 37 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 37 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP38 Process identifier present from bus master 38 6 1 read-only 0 Bus master 38 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 38 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP39 Process identifier present from bus master 39 7 1 read-only 0 Bus master 39 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 39 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP40 Process identifier present from bus master 40 8 1 read-only 0 Bus master 40 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 40 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP41 Process identifier present from bus master 41 9 1 read-only 0 Bus master 41 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 41 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP42 Process identifier present from bus master 42 10 1 read-only 0 Bus master 42 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 42 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP43 Process identifier present from bus master 43 11 1 read-only 0 Bus master 43 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 43 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP44 Process identifier present from bus master 44 12 1 read-only 0 Bus master 44 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 44 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP45 Process identifier present from bus master 45 13 1 read-only 0 Bus master 45 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 45 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP46 Process identifier present from bus master 46 14 1 read-only 0 Bus master 46 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 46 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP47 Process identifier present from bus master 47 15 1 read-only 0 Bus master 47 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 47 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP48 Process identifier present from bus master 48 16 1 read-only 0 Bus master 48 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 48 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP49 Process identifier present from bus master 49 17 1 read-only 0 Bus master 49 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 49 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP50 Process identifier present from bus master 50 18 1 read-only 0 Bus master 50 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 50 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP51 Process identifier present from bus master 51 19 1 read-only 0 Bus master 51 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 51 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP52 Process identifier present from bus master 52 20 1 read-only 0 Bus master 52 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 52 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP53 Process identifier present from bus master 53 21 1 read-only 0 Bus master 53 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 53 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP54 Process identifier present from bus master 54 22 1 read-only 0 Bus master 54 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 54 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP55 Process identifier present from bus master 55 23 1 read-only 0 Bus master 55 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 55sources a process identifier register to the XRDC_MDAC logic. #1 PIDP56 Process identifier present from bus master 56 24 1 read-only 0 Bus master 56 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 56 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP57 Process identifier present from bus master 57 25 1 read-only 0 Bus master 57 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 57 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP58 Process identifier present from bus master 58 26 1 read-only 0 Bus master 58 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 58 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP59 Process identifier present from bus master 59 27 1 read-only 0 Bus master 59 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 59 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP60 Process identifier present from bus master 60 28 1 read-only 0 Bus master 60 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 60 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP61 Process identifier present from bus master 61 29 1 read-only 0 Bus master 61 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 61 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP62 Process identifier present from bus master 62 30 1 read-only 0 Bus master 62 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 62 sources a process identifier register to the XRDC_MDAC logic. #1 PIDP63 Process identifier present from bus master 63 31 1 read-only 0 Bus master 63 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. #0 1 Bus master 63 sources a process identifier register to the XRDC_MDAC logic. #1 MDACFG0 Master Domain Assignment Configuration Register 0x200 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG1 Master Domain Assignment Configuration Register 0x301 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG10 Master Domain Assignment Configuration Register 0xC37 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG11 Master Domain Assignment Configuration Register 0xD42 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG12 Master Domain Assignment Configuration Register 0xE4E 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG13 Master Domain Assignment Configuration Register 0xF5B 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG14 Master Domain Assignment Configuration Register 0x1069 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG15 Master Domain Assignment Configuration Register 0x1178 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG16 Master Domain Assignment Configuration Register 0x1288 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG17 Master Domain Assignment Configuration Register 0x1399 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG18 Master Domain Assignment Configuration Register 0x14AB 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG19 Master Domain Assignment Configuration Register 0x15BE 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG2 Master Domain Assignment Configuration Register 0x403 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG20 Master Domain Assignment Configuration Register 0x16D2 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG21 Master Domain Assignment Configuration Register 0x17E7 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG22 Master Domain Assignment Configuration Register 0x18FD 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG23 Master Domain Assignment Configuration Register 0x1A14 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG24 Master Domain Assignment Configuration Register 0x1B2C 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG25 Master Domain Assignment Configuration Register 0x1C45 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG26 Master Domain Assignment Configuration Register 0x1D5F 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG27 Master Domain Assignment Configuration Register 0x1E7A 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG28 Master Domain Assignment Configuration Register 0x1F96 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG29 Master Domain Assignment Configuration Register 0x20B3 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG3 Master Domain Assignment Configuration Register 0x506 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG30 Master Domain Assignment Configuration Register 0x21D1 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG31 Master Domain Assignment Configuration Register 0x22F0 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG32 Master Domain Assignment Configuration Register 0x2410 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG33 Master Domain Assignment Configuration Register 0x2531 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG34 Master Domain Assignment Configuration Register 0x2653 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG35 Master Domain Assignment Configuration Register 0x2776 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG36 Master Domain Assignment Configuration Register 0x289A 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG37 Master Domain Assignment Configuration Register 0x29BF 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG4 Master Domain Assignment Configuration Register 0x60A 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG5 Master Domain Assignment Configuration Register 0x70F 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG6 Master Domain Assignment Configuration Register 0x815 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG7 Master Domain Assignment Configuration Register 0x91C 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG8 Master Domain Assignment Configuration Register 0xA24 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDACFG9 Master Domain Assignment Configuration Register 0xB2D 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only 0 Bus master is a processor. #0 1 Bus master is a non-processor. #1 NMDAR Number of master domain assignment registers for bus master n 0 4 read-only MDA_W0_0 Master Domain Assignment Wm,n (DFMT=0) 0x800 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_1 Master Domain Assignment Wm,n (DFMT=0) 0x820 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_10 Master Domain Assignment Wm,n (DFMT=0) 0x940 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_11 Master Domain Assignment Wm,n (DFMT=0) 0x960 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_12 Master Domain Assignment Wm,n (DFMT=0) 0x980 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_13 Master Domain Assignment Wm,n (DFMT=0) 0x9A0 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_14 Master Domain Assignment Wm,n (DFMT=0) 0x9C0 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_15 Master Domain Assignment Wm,n (DFMT=0) 0x9E0 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_16 Master Domain Assignment Wm,n (DFMT=0) 0xA00 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_17 Master Domain Assignment Wm,n (DFMT=0) 0xA20 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_18 Master Domain Assignment Wm,n (DFMT=0) 0xA40 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_19 Master Domain Assignment Wm,n (DFMT=0) 0xA60 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_2 Master Domain Assignment Wm,n (DFMT=0) 0x840 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_20 Master Domain Assignment Wm,n (DFMT=0) 0xA80 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_21 Master Domain Assignment Wm,n (DFMT=0) 0xAA0 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_22 Master Domain Assignment Wm,n (DFMT=0) 0xAC0 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_23 Master Domain Assignment Wm,n (DFMT=0) 0xAE0 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_24 Master Domain Assignment Wm,n (DFMT=0) 0xB00 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_25 Master Domain Assignment Wm,n (DFMT=0) 0xB20 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_26 Master Domain Assignment Wm,n (DFMT=0) 0xB40 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_27 Master Domain Assignment Wm,n (DFMT=0) 0xB60 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_28 Master Domain Assignment Wm,n (DFMT=0) 0xB80 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_29 Master Domain Assignment Wm,n (DFMT=0) 0xBA0 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_3 Master Domain Assignment Wm,n (DFMT=0) 0x860 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_30 Master Domain Assignment Wm,n (DFMT=0) 0xBC0 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_31 Master Domain Assignment Wm,n (DFMT=0) 0xBE0 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_32 Master Domain Assignment Wm,n (DFMT=0) 0xC00 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_33 Master Domain Assignment Wm,n (DFMT=0) 0xC20 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_34 Master Domain Assignment Wm,n (DFMT=0) 0xC40 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_35 Master Domain Assignment Wm,n (DFMT=0) 0xC60 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_36 Master Domain Assignment Wm,n (DFMT=0) 0xC80 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_37 Master Domain Assignment Wm,n (DFMT=0) 0xCA0 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_4 Master Domain Assignment Wm,n (DFMT=0) 0x880 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_5 Master Domain Assignment Wm,n (DFMT=0) 0x8A0 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_6 Master Domain Assignment Wm,n (DFMT=0) 0x8C0 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_7 Master Domain Assignment Wm,n (DFMT=0) 0x8E0 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_8 Master Domain Assignment Wm,n (DFMT=0) 0x900 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W0_9 Master Domain Assignment Wm,n (DFMT=0) 0x920 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_0 Master Domain Assignment Wm,n (DFMT=0) 0x804 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_1 Master Domain Assignment Wm,n (DFMT=0) 0x824 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_10 Master Domain Assignment Wm,n (DFMT=0) 0x944 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_11 Master Domain Assignment Wm,n (DFMT=0) 0x964 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_12 Master Domain Assignment Wm,n (DFMT=0) 0x984 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_13 Master Domain Assignment Wm,n (DFMT=0) 0x9A4 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_14 Master Domain Assignment Wm,n (DFMT=0) 0x9C4 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_15 Master Domain Assignment Wm,n (DFMT=0) 0x9E4 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_16 Master Domain Assignment Wm,n (DFMT=0) 0xA04 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_17 Master Domain Assignment Wm,n (DFMT=0) 0xA24 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_18 Master Domain Assignment Wm,n (DFMT=0) 0xA44 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_19 Master Domain Assignment Wm,n (DFMT=0) 0xA64 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_2 Master Domain Assignment Wm,n (DFMT=0) 0x844 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_20 Master Domain Assignment Wm,n (DFMT=0) 0xA84 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_21 Master Domain Assignment Wm,n (DFMT=0) 0xAA4 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_22 Master Domain Assignment Wm,n (DFMT=0) 0xAC4 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_23 Master Domain Assignment Wm,n (DFMT=0) 0xAE4 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_24 Master Domain Assignment Wm,n (DFMT=0) 0xB04 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_25 Master Domain Assignment Wm,n (DFMT=0) 0xB24 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_26 Master Domain Assignment Wm,n (DFMT=0) 0xB44 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_27 Master Domain Assignment Wm,n (DFMT=0) 0xB64 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_28 Master Domain Assignment Wm,n (DFMT=0) 0xB84 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_29 Master Domain Assignment Wm,n (DFMT=0) 0xBA4 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_3 Master Domain Assignment Wm,n (DFMT=0) 0x864 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_30 Master Domain Assignment Wm,n (DFMT=0) 0xBC4 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_31 Master Domain Assignment Wm,n (DFMT=0) 0xBE4 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_32 Master Domain Assignment Wm,n (DFMT=0) 0xC04 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_33 Master Domain Assignment Wm,n (DFMT=0) 0xC24 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_34 Master Domain Assignment Wm,n (DFMT=0) 0xC44 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_35 Master Domain Assignment Wm,n (DFMT=0) 0xC64 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_36 Master Domain Assignment Wm,n (DFMT=0) 0xC84 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_37 Master Domain Assignment Wm,n (DFMT=0) 0xCA4 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_4 Master Domain Assignment Wm,n (DFMT=0) 0x884 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_5 Master Domain Assignment Wm,n (DFMT=0) 0x8A4 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_6 Master Domain Assignment Wm,n (DFMT=0) 0x8C4 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_7 Master Domain Assignment Wm,n (DFMT=0) 0x8E4 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_8 Master Domain Assignment Wm,n (DFMT=0) 0x904 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MDA_W1_9 Master Domain Assignment Wm,n (DFMT=0) 0x924 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write 00 Use MDAn[3:0] as the domain identifier. #00 01 Use the input DID as the domain identifier. #01 10 Use MDAn[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. #10 LK1 1-bit Lock 30 1 read-write 0 Register can be written by any secure privileged write. #0 1 Register is locked (read-only) until the next reset. #1 LPE Logical partition enable 28 1 read-write LPID Logical partition Identifier 24 4 read-write PE Process identifier enable 6 2 read-write 00 No process identifier is included in the domain hit evaluation. #00 01 No process identifier is included in the domain hit evaluation. #01 10 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 2) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #10 11 The process identifier is included in the domain hit evaluation as defined by the expression: partial_domain_hit = (PE == 3) && ((PID & ~PIDM) == (XRDC_PIDn[PID] & ~PIDM)) #11 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write 0 The Wm domain assignment is invalid. #0 1 The Wm domain assignment is valid. #1 MRCFG0 Memory Region Configuration Register 0x280 8 read-only n 0x0 0x0 NMGD Number of memory region descriptors for MRC i 0 5 read-only MRCFG1 Memory Region Configuration Register 0x3C1 8 read-only n 0x0 0x0 NMGD Number of memory region descriptors for MRC i 0 5 read-only MRGD_W0_0 Memory Region Descriptor W0 0x4000 32 read-write n 0x0 0x0 BASEADDR Base Address 5 27 read-write MRGD_W0_1 Memory Region Descriptor W0 0x6020 32 read-write n 0x0 0x0 BASEADDR Base Address 5 27 read-write MRGD_W0_10 Memory Region Descriptor W0 0x186E0 32 read-write n 0x0 0x0 BASEADDR Base Address 5 27 read-write MRGD_W0_11 Memory Region Descriptor W0 0x1A840 32 read-write n 0x0 0x0 BASEADDR Base Address 5 27 read-write MRGD_W0_12 Memory Region Descriptor W0 0x1C9C0 32 read-write n 0x0 0x0 BASEADDR Base Address 5 27 read-write MRGD_W0_13 Memory Region Descriptor W0 0x1EB60 32 read-write n 0x0 0x0 BASEADDR Base Address 5 27 read-write MRGD_W0_14 Memory Region Descriptor W0 0x20D20 32 read-write n 0x0 0x0 BASEADDR Base Address 5 27 read-write MRGD_W0_15 Memory Region Descriptor W0 0x22F00 32 read-write n 0x0 0x0 BASEADDR Base Address 5 27 read-write MRGD_W0_16 Memory Region Descriptor W0 0x25100 32 read-write n 0x0 0x0 BASEADDR Base Address 5 27 read-write MRGD_W0_17 Memory Region Descriptor W0 0x27320 32 read-write n 0x0 0x0 BASEADDR Base Address 5 27 read-write MRGD_W0_18 Memory Region Descriptor W0 0x29560 32 read-write n 0x0 0x0 BASEADDR Base Address 5 27 read-write MRGD_W0_19 Memory Region Descriptor W0 0x2B7C0 32 read-write n 0x0 0x0 BASEADDR Base Address 5 27 read-write MRGD_W0_2 Memory Region Descriptor W0 0x8060 32 read-write n 0x0 0x0 BASEADDR Base Address 5 27 read-write MRGD_W0_20 Memory Region Descriptor W0 0x2DA40 32 read-write n 0x0 0x0 BASEADDR Base Address 5 27 read-write MRGD_W0_21 Memory Region Descriptor W0 0x2FCE0 32 read-write n 0x0 0x0 BASEADDR Base Address 5 27 read-write MRGD_W0_22 Memory Region Descriptor W0 0x31FA0 32 read-write n 0x0 0x0 BASEADDR Base Address 5 27 read-write MRGD_W0_23 Memory Region Descriptor W0 0x34280 32 read-write n 0x0 0x0 BASEADDR Base Address 5 27 read-write MRGD_W0_3 Memory Region Descriptor W0 0xA0C0 32 read-write n 0x0 0x0 BASEADDR Base Address 5 27 read-write MRGD_W0_4 Memory Region Descriptor W0 0xC140 32 read-write n 0x0 0x0 BASEADDR Base Address 5 27 read-write MRGD_W0_5 Memory Region Descriptor W0 0xE1E0 32 read-write n 0x0 0x0 BASEADDR Base Address 5 27 read-write MRGD_W0_6 Memory Region Descriptor W0 0x102A0 32 read-write n 0x0 0x0 BASEADDR Base Address 5 27 read-write MRGD_W0_7 Memory Region Descriptor W0 0x12380 32 read-write n 0x0 0x0 BASEADDR Base Address 5 27 read-write MRGD_W0_8 Memory Region Descriptor W0 0x14480 32 read-write n 0x0 0x0 BASEADDR Base Address 5 27 read-write MRGD_W0_9 Memory Region Descriptor W0 0x165A0 32 read-write n 0x0 0x0 BASEADDR Base Address 5 27 read-write MRGD_W1_0 Memory Region Descriptor W1 0x4008 32 read-write n 0x0 0x0 SRD Subregion disable 0 8 read-write SZ Region size 8 5 read-write MRGD_W1_1 Memory Region Descriptor W1 0x602C 32 read-write n 0x0 0x0 SRD Subregion disable 0 8 read-write SZ Region size 8 5 read-write MRGD_W1_10 Memory Region Descriptor W1 0x18710 32 read-write n 0x0 0x0 SRD Subregion disable 0 8 read-write SZ Region size 8 5 read-write MRGD_W1_11 Memory Region Descriptor W1 0x1A874 32 read-write n 0x0 0x0 SRD Subregion disable 0 8 read-write SZ Region size 8 5 read-write MRGD_W1_12 Memory Region Descriptor W1 0x1C9F8 32 read-write n 0x0 0x0 SRD Subregion disable 0 8 read-write SZ Region size 8 5 read-write MRGD_W1_13 Memory Region Descriptor W1 0x1EB9C 32 read-write n 0x0 0x0 SRD Subregion disable 0 8 read-write SZ Region size 8 5 read-write MRGD_W1_14 Memory Region Descriptor W1 0x20D60 32 read-write n 0x0 0x0 SRD Subregion disable 0 8 read-write SZ Region size 8 5 read-write MRGD_W1_15 Memory Region Descriptor W1 0x22F44 32 read-write n 0x0 0x0 SRD Subregion disable 0 8 read-write SZ Region size 8 5 read-write MRGD_W1_16 Memory Region Descriptor W1 0x25148 32 read-write n 0x0 0x0 SRD Subregion disable 0 8 read-write SZ Region size 8 5 read-write MRGD_W1_17 Memory Region Descriptor W1 0x2736C 32 read-write n 0x0 0x0 SRD Subregion disable 0 8 read-write SZ Region size 8 5 read-write MRGD_W1_18 Memory Region Descriptor W1 0x295B0 32 read-write n 0x0 0x0 SRD Subregion disable 0 8 read-write SZ Region size 8 5 read-write MRGD_W1_19 Memory Region Descriptor W1 0x2B814 32 read-write n 0x0 0x0 SRD Subregion disable 0 8 read-write SZ Region size 8 5 read-write MRGD_W1_2 Memory Region Descriptor W1 0x8070 32 read-write n 0x0 0x0 SRD Subregion disable 0 8 read-write SZ Region size 8 5 read-write MRGD_W1_20 Memory Region Descriptor W1 0x2DA98 32 read-write n 0x0 0x0 SRD Subregion disable 0 8 read-write SZ Region size 8 5 read-write MRGD_W1_21 Memory Region Descriptor W1 0x2FD3C 32 read-write n 0x0 0x0 SRD Subregion disable 0 8 read-write SZ Region size 8 5 read-write MRGD_W1_22 Memory Region Descriptor W1 0x32000 32 read-write n 0x0 0x0 SRD Subregion disable 0 8 read-write SZ Region size 8 5 read-write MRGD_W1_23 Memory Region Descriptor W1 0x342E4 32 read-write n 0x0 0x0 SRD Subregion disable 0 8 read-write SZ Region size 8 5 read-write MRGD_W1_3 Memory Region Descriptor W1 0xA0D4 32 read-write n 0x0 0x0 SRD Subregion disable 0 8 read-write SZ Region size 8 5 read-write MRGD_W1_4 Memory Region Descriptor W1 0xC158 32 read-write n 0x0 0x0 SRD Subregion disable 0 8 read-write SZ Region size 8 5 read-write MRGD_W1_5 Memory Region Descriptor W1 0xE1FC 32 read-write n 0x0 0x0 SRD Subregion disable 0 8 read-write SZ Region size 8 5 read-write MRGD_W1_6 Memory Region Descriptor W1 0x102C0 32 read-write n 0x0 0x0 SRD Subregion disable 0 8 read-write SZ Region size 8 5 read-write MRGD_W1_7 Memory Region Descriptor W1 0x123A4 32 read-write n 0x0 0x0 SRD Subregion disable 0 8 read-write SZ Region size 8 5 read-write MRGD_W1_8 Memory Region Descriptor W1 0x144A8 32 read-write n 0x0 0x0 SRD Subregion disable 0 8 read-write SZ Region size 8 5 read-write MRGD_W1_9 Memory Region Descriptor W1 0x165CC 32 read-write n 0x0 0x0 SRD Subregion disable 0 8 read-write SZ Region size 8 5 read-write MRGD_W2_0 Memory Region Descriptor W2 0x4010 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W2[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write MRGD_W2_1 Memory Region Descriptor W2 0x6038 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W2[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write MRGD_W2_10 Memory Region Descriptor W2 0x18740 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W2[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write MRGD_W2_11 Memory Region Descriptor W2 0x1A8A8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W2[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write MRGD_W2_12 Memory Region Descriptor W2 0x1CA30 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W2[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write MRGD_W2_13 Memory Region Descriptor W2 0x1EBD8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W2[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write MRGD_W2_14 Memory Region Descriptor W2 0x20DA0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W2[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write MRGD_W2_15 Memory Region Descriptor W2 0x22F88 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W2[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write MRGD_W2_16 Memory Region Descriptor W2 0x25190 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W2[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write MRGD_W2_17 Memory Region Descriptor W2 0x273B8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W2[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write MRGD_W2_18 Memory Region Descriptor W2 0x29600 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W2[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write MRGD_W2_19 Memory Region Descriptor W2 0x2B868 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W2[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write MRGD_W2_2 Memory Region Descriptor W2 0x8080 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W2[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write MRGD_W2_20 Memory Region Descriptor W2 0x2DAF0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W2[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write MRGD_W2_21 Memory Region Descriptor W2 0x2FD98 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W2[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write MRGD_W2_22 Memory Region Descriptor W2 0x32060 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W2[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write MRGD_W2_23 Memory Region Descriptor W2 0x34348 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W2[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write MRGD_W2_3 Memory Region Descriptor W2 0xA0E8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W2[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write MRGD_W2_4 Memory Region Descriptor W2 0xC170 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W2[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write MRGD_W2_5 Memory Region Descriptor W2 0xE218 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W2[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write MRGD_W2_6 Memory Region Descriptor W2 0x102E0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W2[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write MRGD_W2_7 Memory Region Descriptor W2 0x123C8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W2[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write MRGD_W2_8 Memory Region Descriptor W2 0x144D0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W2[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write MRGD_W2_9 Memory Region Descriptor W2 0x165F8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W2[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write MRGD_W3_0 Memory Region Descriptor W3 0x4018 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire MRGDn can be written. #00 01 Entire MRGDn can be written. #01 10 Domain "x" can only update the DxACP field; no other MRGDn fields can be written #10 11 MRGDn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write MRGD_W3_1 Memory Region Descriptor W3 0x6044 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire MRGDn can be written. #00 01 Entire MRGDn can be written. #01 10 Domain "x" can only update the DxACP field; no other MRGDn fields can be written #10 11 MRGDn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write MRGD_W3_10 Memory Region Descriptor W3 0x18770 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire MRGDn can be written. #00 01 Entire MRGDn can be written. #01 10 Domain "x" can only update the DxACP field; no other MRGDn fields can be written #10 11 MRGDn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write MRGD_W3_11 Memory Region Descriptor W3 0x1A8DC 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire MRGDn can be written. #00 01 Entire MRGDn can be written. #01 10 Domain "x" can only update the DxACP field; no other MRGDn fields can be written #10 11 MRGDn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write MRGD_W3_12 Memory Region Descriptor W3 0x1CA68 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire MRGDn can be written. #00 01 Entire MRGDn can be written. #01 10 Domain "x" can only update the DxACP field; no other MRGDn fields can be written #10 11 MRGDn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write MRGD_W3_13 Memory Region Descriptor W3 0x1EC14 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire MRGDn can be written. #00 01 Entire MRGDn can be written. #01 10 Domain "x" can only update the DxACP field; no other MRGDn fields can be written #10 11 MRGDn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write MRGD_W3_14 Memory Region Descriptor W3 0x20DE0 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire MRGDn can be written. #00 01 Entire MRGDn can be written. #01 10 Domain "x" can only update the DxACP field; no other MRGDn fields can be written #10 11 MRGDn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write MRGD_W3_15 Memory Region Descriptor W3 0x22FCC 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire MRGDn can be written. #00 01 Entire MRGDn can be written. #01 10 Domain "x" can only update the DxACP field; no other MRGDn fields can be written #10 11 MRGDn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write MRGD_W3_16 Memory Region Descriptor W3 0x251D8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire MRGDn can be written. #00 01 Entire MRGDn can be written. #01 10 Domain "x" can only update the DxACP field; no other MRGDn fields can be written #10 11 MRGDn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write MRGD_W3_17 Memory Region Descriptor W3 0x27404 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire MRGDn can be written. #00 01 Entire MRGDn can be written. #01 10 Domain "x" can only update the DxACP field; no other MRGDn fields can be written #10 11 MRGDn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write MRGD_W3_18 Memory Region Descriptor W3 0x29650 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire MRGDn can be written. #00 01 Entire MRGDn can be written. #01 10 Domain "x" can only update the DxACP field; no other MRGDn fields can be written #10 11 MRGDn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write MRGD_W3_19 Memory Region Descriptor W3 0x2B8BC 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire MRGDn can be written. #00 01 Entire MRGDn can be written. #01 10 Domain "x" can only update the DxACP field; no other MRGDn fields can be written #10 11 MRGDn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write MRGD_W3_2 Memory Region Descriptor W3 0x8090 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire MRGDn can be written. #00 01 Entire MRGDn can be written. #01 10 Domain "x" can only update the DxACP field; no other MRGDn fields can be written #10 11 MRGDn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write MRGD_W3_20 Memory Region Descriptor W3 0x2DB48 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire MRGDn can be written. #00 01 Entire MRGDn can be written. #01 10 Domain "x" can only update the DxACP field; no other MRGDn fields can be written #10 11 MRGDn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write MRGD_W3_21 Memory Region Descriptor W3 0x2FDF4 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire MRGDn can be written. #00 01 Entire MRGDn can be written. #01 10 Domain "x" can only update the DxACP field; no other MRGDn fields can be written #10 11 MRGDn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write MRGD_W3_22 Memory Region Descriptor W3 0x320C0 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire MRGDn can be written. #00 01 Entire MRGDn can be written. #01 10 Domain "x" can only update the DxACP field; no other MRGDn fields can be written #10 11 MRGDn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write MRGD_W3_23 Memory Region Descriptor W3 0x343AC 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire MRGDn can be written. #00 01 Entire MRGDn can be written. #01 10 Domain "x" can only update the DxACP field; no other MRGDn fields can be written #10 11 MRGDn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write MRGD_W3_3 Memory Region Descriptor W3 0xA0FC 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire MRGDn can be written. #00 01 Entire MRGDn can be written. #01 10 Domain "x" can only update the DxACP field; no other MRGDn fields can be written #10 11 MRGDn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write MRGD_W3_4 Memory Region Descriptor W3 0xC188 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire MRGDn can be written. #00 01 Entire MRGDn can be written. #01 10 Domain "x" can only update the DxACP field; no other MRGDn fields can be written #10 11 MRGDn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write MRGD_W3_5 Memory Region Descriptor W3 0xE234 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire MRGDn can be written. #00 01 Entire MRGDn can be written. #01 10 Domain "x" can only update the DxACP field; no other MRGDn fields can be written #10 11 MRGDn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write MRGD_W3_6 Memory Region Descriptor W3 0x10300 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire MRGDn can be written. #00 01 Entire MRGDn can be written. #01 10 Domain "x" can only update the DxACP field; no other MRGDn fields can be written #10 11 MRGDn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write MRGD_W3_7 Memory Region Descriptor W3 0x123EC 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire MRGDn can be written. #00 01 Entire MRGDn can be written. #01 10 Domain "x" can only update the DxACP field; no other MRGDn fields can be written #10 11 MRGDn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write MRGD_W3_8 Memory Region Descriptor W3 0x144F8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire MRGDn can be written. #00 01 Entire MRGDn can be written. #01 10 Domain "x" can only update the DxACP field; no other MRGDn fields can be written #10 11 MRGDn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write MRGD_W3_9 Memory Region Descriptor W3 0x16624 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire MRGDn can be written. #00 01 Entire MRGDn can be written. #01 10 Domain "x" can only update the DxACP field; no other MRGDn fields can be written #10 11 MRGDn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write MRGD_W4_0 Memory Region Descriptor W4 0x4020 32 read-only n 0x0 0x0 MRGD_W4_1 Memory Region Descriptor W4 0x6050 32 read-only n 0x0 0x0 MRGD_W4_10 Memory Region Descriptor W4 0x187A0 32 read-only n 0x0 0x0 MRGD_W4_11 Memory Region Descriptor W4 0x1A910 32 read-only n 0x0 0x0 MRGD_W4_12 Memory Region Descriptor W4 0x1CAA0 32 read-only n 0x0 0x0 MRGD_W4_13 Memory Region Descriptor W4 0x1EC50 32 read-only n 0x0 0x0 MRGD_W4_14 Memory Region Descriptor W4 0x20E20 32 read-only n 0x0 0x0 MRGD_W4_15 Memory Region Descriptor W4 0x23010 32 read-only n 0x0 0x0 MRGD_W4_16 Memory Region Descriptor W4 0x25220 32 read-only n 0x0 0x0 MRGD_W4_17 Memory Region Descriptor W4 0x27450 32 read-only n 0x0 0x0 MRGD_W4_18 Memory Region Descriptor W4 0x296A0 32 read-only n 0x0 0x0 MRGD_W4_19 Memory Region Descriptor W4 0x2B910 32 read-only n 0x0 0x0 MRGD_W4_2 Memory Region Descriptor W4 0x80A0 32 read-only n 0x0 0x0 MRGD_W4_20 Memory Region Descriptor W4 0x2DBA0 32 read-only n 0x0 0x0 MRGD_W4_21 Memory Region Descriptor W4 0x2FE50 32 read-only n 0x0 0x0 MRGD_W4_22 Memory Region Descriptor W4 0x32120 32 read-only n 0x0 0x0 MRGD_W4_23 Memory Region Descriptor W4 0x34410 32 read-only n 0x0 0x0 MRGD_W4_3 Memory Region Descriptor W4 0xA110 32 read-only n 0x0 0x0 MRGD_W4_4 Memory Region Descriptor W4 0xC1A0 32 read-only n 0x0 0x0 MRGD_W4_5 Memory Region Descriptor W4 0xE250 32 read-only n 0x0 0x0 MRGD_W4_6 Memory Region Descriptor W4 0x10320 32 read-only n 0x0 0x0 MRGD_W4_7 Memory Region Descriptor W4 0x12410 32 read-only n 0x0 0x0 MRGD_W4_8 Memory Region Descriptor W4 0x14520 32 read-only n 0x0 0x0 MRGD_W4_9 Memory Region Descriptor W4 0x16650 32 read-only n 0x0 0x0 MRGD_W5_0 Memory Region Descriptor W5 0x4028 32 read-only n 0x0 0x0 MRGD_W5_1 Memory Region Descriptor W5 0x605C 32 read-only n 0x0 0x0 MRGD_W5_10 Memory Region Descriptor W5 0x187D0 32 read-only n 0x0 0x0 MRGD_W5_11 Memory Region Descriptor W5 0x1A944 32 read-only n 0x0 0x0 MRGD_W5_12 Memory Region Descriptor W5 0x1CAD8 32 read-only n 0x0 0x0 MRGD_W5_13 Memory Region Descriptor W5 0x1EC8C 32 read-only n 0x0 0x0 MRGD_W5_14 Memory Region Descriptor W5 0x20E60 32 read-only n 0x0 0x0 MRGD_W5_15 Memory Region Descriptor W5 0x23054 32 read-only n 0x0 0x0 MRGD_W5_16 Memory Region Descriptor W5 0x25268 32 read-only n 0x0 0x0 MRGD_W5_17 Memory Region Descriptor W5 0x2749C 32 read-only n 0x0 0x0 MRGD_W5_18 Memory Region Descriptor W5 0x296F0 32 read-only n 0x0 0x0 MRGD_W5_19 Memory Region Descriptor W5 0x2B964 32 read-only n 0x0 0x0 MRGD_W5_2 Memory Region Descriptor W5 0x80B0 32 read-only n 0x0 0x0 MRGD_W5_20 Memory Region Descriptor W5 0x2DBF8 32 read-only n 0x0 0x0 MRGD_W5_21 Memory Region Descriptor W5 0x2FEAC 32 read-only n 0x0 0x0 MRGD_W5_22 Memory Region Descriptor W5 0x32180 32 read-only n 0x0 0x0 MRGD_W5_23 Memory Region Descriptor W5 0x34474 32 read-only n 0x0 0x0 MRGD_W5_3 Memory Region Descriptor W5 0xA124 32 read-only n 0x0 0x0 MRGD_W5_4 Memory Region Descriptor W5 0xC1B8 32 read-only n 0x0 0x0 MRGD_W5_5 Memory Region Descriptor W5 0xE26C 32 read-only n 0x0 0x0 MRGD_W5_6 Memory Region Descriptor W5 0x10340 32 read-only n 0x0 0x0 MRGD_W5_7 Memory Region Descriptor W5 0x12434 32 read-only n 0x0 0x0 MRGD_W5_8 Memory Region Descriptor W5 0x14548 32 read-only n 0x0 0x0 MRGD_W5_9 Memory Region Descriptor W5 0x1667C 32 read-only n 0x0 0x0 MRGD_W6_0 Memory Region Descriptor W6 0x4030 32 read-only n 0x0 0x0 MRGD_W6_1 Memory Region Descriptor W6 0x6068 32 read-only n 0x0 0x0 MRGD_W6_10 Memory Region Descriptor W6 0x18800 32 read-only n 0x0 0x0 MRGD_W6_11 Memory Region Descriptor W6 0x1A978 32 read-only n 0x0 0x0 MRGD_W6_12 Memory Region Descriptor W6 0x1CB10 32 read-only n 0x0 0x0 MRGD_W6_13 Memory Region Descriptor W6 0x1ECC8 32 read-only n 0x0 0x0 MRGD_W6_14 Memory Region Descriptor W6 0x20EA0 32 read-only n 0x0 0x0 MRGD_W6_15 Memory Region Descriptor W6 0x23098 32 read-only n 0x0 0x0 MRGD_W6_16 Memory Region Descriptor W6 0x252B0 32 read-only n 0x0 0x0 MRGD_W6_17 Memory Region Descriptor W6 0x274E8 32 read-only n 0x0 0x0 MRGD_W6_18 Memory Region Descriptor W6 0x29740 32 read-only n 0x0 0x0 MRGD_W6_19 Memory Region Descriptor W6 0x2B9B8 32 read-only n 0x0 0x0 MRGD_W6_2 Memory Region Descriptor W6 0x80C0 32 read-only n 0x0 0x0 MRGD_W6_20 Memory Region Descriptor W6 0x2DC50 32 read-only n 0x0 0x0 MRGD_W6_21 Memory Region Descriptor W6 0x2FF08 32 read-only n 0x0 0x0 MRGD_W6_22 Memory Region Descriptor W6 0x321E0 32 read-only n 0x0 0x0 MRGD_W6_23 Memory Region Descriptor W6 0x344D8 32 read-only n 0x0 0x0 MRGD_W6_3 Memory Region Descriptor W6 0xA138 32 read-only n 0x0 0x0 MRGD_W6_4 Memory Region Descriptor W6 0xC1D0 32 read-only n 0x0 0x0 MRGD_W6_5 Memory Region Descriptor W6 0xE288 32 read-only n 0x0 0x0 MRGD_W6_6 Memory Region Descriptor W6 0x10360 32 read-only n 0x0 0x0 MRGD_W6_7 Memory Region Descriptor W6 0x12458 32 read-only n 0x0 0x0 MRGD_W6_8 Memory Region Descriptor W6 0x14570 32 read-only n 0x0 0x0 MRGD_W6_9 Memory Region Descriptor W6 0x166A8 32 read-only n 0x0 0x0 MRGD_W7_0 Memory Region Descriptor W7 0x4038 32 read-only n 0x0 0x0 MRGD_W7_1 Memory Region Descriptor W7 0x6074 32 read-only n 0x0 0x0 MRGD_W7_10 Memory Region Descriptor W7 0x18830 32 read-only n 0x0 0x0 MRGD_W7_11 Memory Region Descriptor W7 0x1A9AC 32 read-only n 0x0 0x0 MRGD_W7_12 Memory Region Descriptor W7 0x1CB48 32 read-only n 0x0 0x0 MRGD_W7_13 Memory Region Descriptor W7 0x1ED04 32 read-only n 0x0 0x0 MRGD_W7_14 Memory Region Descriptor W7 0x20EE0 32 read-only n 0x0 0x0 MRGD_W7_15 Memory Region Descriptor W7 0x230DC 32 read-only n 0x0 0x0 MRGD_W7_16 Memory Region Descriptor W7 0x252F8 32 read-only n 0x0 0x0 MRGD_W7_17 Memory Region Descriptor W7 0x27534 32 read-only n 0x0 0x0 MRGD_W7_18 Memory Region Descriptor W7 0x29790 32 read-only n 0x0 0x0 MRGD_W7_19 Memory Region Descriptor W7 0x2BA0C 32 read-only n 0x0 0x0 MRGD_W7_2 Memory Region Descriptor W7 0x80D0 32 read-only n 0x0 0x0 MRGD_W7_20 Memory Region Descriptor W7 0x2DCA8 32 read-only n 0x0 0x0 MRGD_W7_21 Memory Region Descriptor W7 0x2FF64 32 read-only n 0x0 0x0 MRGD_W7_22 Memory Region Descriptor W7 0x32240 32 read-only n 0x0 0x0 MRGD_W7_23 Memory Region Descriptor W7 0x3453C 32 read-only n 0x0 0x0 MRGD_W7_3 Memory Region Descriptor W7 0xA14C 32 read-only n 0x0 0x0 MRGD_W7_4 Memory Region Descriptor W7 0xC1E8 32 read-only n 0x0 0x0 MRGD_W7_5 Memory Region Descriptor W7 0xE2A4 32 read-only n 0x0 0x0 MRGD_W7_6 Memory Region Descriptor W7 0x10380 32 read-only n 0x0 0x0 MRGD_W7_7 Memory Region Descriptor W7 0x1247C 32 read-only n 0x0 0x0 MRGD_W7_8 Memory Region Descriptor W7 0x14598 32 read-only n 0x0 0x0 MRGD_W7_9 Memory Region Descriptor W7 0x166D4 32 read-only n 0x0 0x0 PDAC_W0_0 Peripheral Domain Access Control W0 0x2000 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_1 Peripheral Domain Access Control W0 0x3008 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_10 Peripheral Domain Access Control W0 0xC1B8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_100 Peripheral Domain Access Control W0 0x6FDD0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_101 Peripheral Domain Access Control W0 0x710F8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_102 Peripheral Domain Access Control W0 0x72428 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_103 Peripheral Domain Access Control W0 0x73760 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_104 Peripheral Domain Access Control W0 0x74AA0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_105 Peripheral Domain Access Control W0 0x75DE8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_106 Peripheral Domain Access Control W0 0x77138 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_107 Peripheral Domain Access Control W0 0x78490 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_108 Peripheral Domain Access Control W0 0x797F0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_109 Peripheral Domain Access Control W0 0x7AB58 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_11 Peripheral Domain Access Control W0 0xD210 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_110 Peripheral Domain Access Control W0 0x7BEC8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_111 Peripheral Domain Access Control W0 0x7D240 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_112 Peripheral Domain Access Control W0 0x7E5C0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_113 Peripheral Domain Access Control W0 0x7F948 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_114 Peripheral Domain Access Control W0 0x80CD8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_115 Peripheral Domain Access Control W0 0x82070 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_116 Peripheral Domain Access Control W0 0x83410 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_117 Peripheral Domain Access Control W0 0x847B8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_118 Peripheral Domain Access Control W0 0x85B68 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_119 Peripheral Domain Access Control W0 0x86F20 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_12 Peripheral Domain Access Control W0 0xE270 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_120 Peripheral Domain Access Control W0 0x882E0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_121 Peripheral Domain Access Control W0 0x896A8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_122 Peripheral Domain Access Control W0 0x8AA78 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_123 Peripheral Domain Access Control W0 0x8BE50 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_124 Peripheral Domain Access Control W0 0x8D230 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_125 Peripheral Domain Access Control W0 0x8E618 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_126 Peripheral Domain Access Control W0 0x8FA08 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_127 Peripheral Domain Access Control W0 0x90E00 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_128 Peripheral Domain Access Control W0 0x92200 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_129 Peripheral Domain Access Control W0 0x93608 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_13 Peripheral Domain Access Control W0 0xF2D8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_130 Peripheral Domain Access Control W0 0x94A18 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_131 Peripheral Domain Access Control W0 0x95E30 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_132 Peripheral Domain Access Control W0 0x97250 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_133 Peripheral Domain Access Control W0 0x98678 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_134 Peripheral Domain Access Control W0 0x99AA8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_135 Peripheral Domain Access Control W0 0x9AEE0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_136 Peripheral Domain Access Control W0 0x9C320 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_137 Peripheral Domain Access Control W0 0x9D768 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_138 Peripheral Domain Access Control W0 0x9EBB8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_139 Peripheral Domain Access Control W0 0xA0010 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_14 Peripheral Domain Access Control W0 0x10348 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_140 Peripheral Domain Access Control W0 0xA1470 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_141 Peripheral Domain Access Control W0 0xA28D8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_142 Peripheral Domain Access Control W0 0xA3D48 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_143 Peripheral Domain Access Control W0 0xA51C0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_144 Peripheral Domain Access Control W0 0xA6640 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_145 Peripheral Domain Access Control W0 0xA7AC8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_146 Peripheral Domain Access Control W0 0xA8F58 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_147 Peripheral Domain Access Control W0 0xAA3F0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_148 Peripheral Domain Access Control W0 0xAB890 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_149 Peripheral Domain Access Control W0 0xACD38 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_15 Peripheral Domain Access Control W0 0x113C0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_150 Peripheral Domain Access Control W0 0xAE1E8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_151 Peripheral Domain Access Control W0 0xAF6A0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_152 Peripheral Domain Access Control W0 0xB0B60 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_153 Peripheral Domain Access Control W0 0xB2028 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_154 Peripheral Domain Access Control W0 0xB34F8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_155 Peripheral Domain Access Control W0 0xB49D0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_156 Peripheral Domain Access Control W0 0xB5EB0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_157 Peripheral Domain Access Control W0 0xB7398 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_158 Peripheral Domain Access Control W0 0xB8888 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_159 Peripheral Domain Access Control W0 0xB9D80 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_16 Peripheral Domain Access Control W0 0x12440 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_160 Peripheral Domain Access Control W0 0xBB280 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_161 Peripheral Domain Access Control W0 0xBC788 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_162 Peripheral Domain Access Control W0 0xBDC98 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_163 Peripheral Domain Access Control W0 0xBF1B0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_164 Peripheral Domain Access Control W0 0xC06D0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_165 Peripheral Domain Access Control W0 0xC1BF8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_166 Peripheral Domain Access Control W0 0xC3128 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_167 Peripheral Domain Access Control W0 0xC4660 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_168 Peripheral Domain Access Control W0 0xC5BA0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_169 Peripheral Domain Access Control W0 0xC70E8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_17 Peripheral Domain Access Control W0 0x134C8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_170 Peripheral Domain Access Control W0 0xC8638 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_171 Peripheral Domain Access Control W0 0xC9B90 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_172 Peripheral Domain Access Control W0 0xCB0F0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_173 Peripheral Domain Access Control W0 0xCC658 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_174 Peripheral Domain Access Control W0 0xCDBC8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_175 Peripheral Domain Access Control W0 0xCF140 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_176 Peripheral Domain Access Control W0 0xD06C0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_177 Peripheral Domain Access Control W0 0xD1C48 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_178 Peripheral Domain Access Control W0 0xD31D8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_179 Peripheral Domain Access Control W0 0xD4770 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_18 Peripheral Domain Access Control W0 0x14558 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_180 Peripheral Domain Access Control W0 0xD5D10 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_181 Peripheral Domain Access Control W0 0xD72B8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_182 Peripheral Domain Access Control W0 0xD8868 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_183 Peripheral Domain Access Control W0 0xD9E20 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_184 Peripheral Domain Access Control W0 0xDB3E0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_185 Peripheral Domain Access Control W0 0xDC9A8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_186 Peripheral Domain Access Control W0 0xDDF78 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_187 Peripheral Domain Access Control W0 0xDF550 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_188 Peripheral Domain Access Control W0 0xE0B30 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_189 Peripheral Domain Access Control W0 0xE2118 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_19 Peripheral Domain Access Control W0 0x155F0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_190 Peripheral Domain Access Control W0 0xE3708 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_191 Peripheral Domain Access Control W0 0xE4D00 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_192 Peripheral Domain Access Control W0 0xE6300 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_193 Peripheral Domain Access Control W0 0xE7908 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_194 Peripheral Domain Access Control W0 0xE8F18 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_195 Peripheral Domain Access Control W0 0xEA530 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_196 Peripheral Domain Access Control W0 0xEBB50 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_197 Peripheral Domain Access Control W0 0xED178 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_198 Peripheral Domain Access Control W0 0xEE7A8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_199 Peripheral Domain Access Control W0 0xEFDE0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_2 Peripheral Domain Access Control W0 0x4018 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_20 Peripheral Domain Access Control W0 0x16690 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_200 Peripheral Domain Access Control W0 0xF1420 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_201 Peripheral Domain Access Control W0 0xF2A68 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_202 Peripheral Domain Access Control W0 0xF40B8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_203 Peripheral Domain Access Control W0 0xF5710 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_204 Peripheral Domain Access Control W0 0xF6D70 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_205 Peripheral Domain Access Control W0 0xF83D8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_206 Peripheral Domain Access Control W0 0xF9A48 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_207 Peripheral Domain Access Control W0 0xFB0C0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_208 Peripheral Domain Access Control W0 0xFC740 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_209 Peripheral Domain Access Control W0 0xFDDC8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_21 Peripheral Domain Access Control W0 0x17738 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_210 Peripheral Domain Access Control W0 0xFF458 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_211 Peripheral Domain Access Control W0 0x100AF0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_212 Peripheral Domain Access Control W0 0x102190 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_213 Peripheral Domain Access Control W0 0x103838 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_214 Peripheral Domain Access Control W0 0x104EE8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_215 Peripheral Domain Access Control W0 0x1065A0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_216 Peripheral Domain Access Control W0 0x107C60 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_217 Peripheral Domain Access Control W0 0x109328 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_218 Peripheral Domain Access Control W0 0x10A9F8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_219 Peripheral Domain Access Control W0 0x10C0D0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_22 Peripheral Domain Access Control W0 0x187E8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_220 Peripheral Domain Access Control W0 0x10D7B0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_221 Peripheral Domain Access Control W0 0x10EE98 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_222 Peripheral Domain Access Control W0 0x110588 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_223 Peripheral Domain Access Control W0 0x111C80 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_224 Peripheral Domain Access Control W0 0x113380 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_225 Peripheral Domain Access Control W0 0x114A88 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_226 Peripheral Domain Access Control W0 0x116198 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_227 Peripheral Domain Access Control W0 0x1178B0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_228 Peripheral Domain Access Control W0 0x118FD0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_229 Peripheral Domain Access Control W0 0x11A6F8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_23 Peripheral Domain Access Control W0 0x198A0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_230 Peripheral Domain Access Control W0 0x11BE28 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_231 Peripheral Domain Access Control W0 0x11D560 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_232 Peripheral Domain Access Control W0 0x11ECA0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_233 Peripheral Domain Access Control W0 0x1203E8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_234 Peripheral Domain Access Control W0 0x121B38 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_235 Peripheral Domain Access Control W0 0x123290 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_236 Peripheral Domain Access Control W0 0x1249F0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_237 Peripheral Domain Access Control W0 0x126158 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_238 Peripheral Domain Access Control W0 0x1278C8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_239 Peripheral Domain Access Control W0 0x129040 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_24 Peripheral Domain Access Control W0 0x1A960 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_240 Peripheral Domain Access Control W0 0x12A7C0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_241 Peripheral Domain Access Control W0 0x12BF48 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_242 Peripheral Domain Access Control W0 0x12D6D8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_243 Peripheral Domain Access Control W0 0x12EE70 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_244 Peripheral Domain Access Control W0 0x130610 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_245 Peripheral Domain Access Control W0 0x131DB8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_246 Peripheral Domain Access Control W0 0x133568 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_247 Peripheral Domain Access Control W0 0x134D20 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_248 Peripheral Domain Access Control W0 0x1364E0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_249 Peripheral Domain Access Control W0 0x137CA8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_25 Peripheral Domain Access Control W0 0x1BA28 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_250 Peripheral Domain Access Control W0 0x139478 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_251 Peripheral Domain Access Control W0 0x13AC50 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_252 Peripheral Domain Access Control W0 0x13C430 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_253 Peripheral Domain Access Control W0 0x13DC18 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_254 Peripheral Domain Access Control W0 0x13F408 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_255 Peripheral Domain Access Control W0 0x140C00 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_256 Peripheral Domain Access Control W0 0x142400 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_26 Peripheral Domain Access Control W0 0x1CAF8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_27 Peripheral Domain Access Control W0 0x1DBD0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_28 Peripheral Domain Access Control W0 0x1ECB0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_29 Peripheral Domain Access Control W0 0x1FD98 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_3 Peripheral Domain Access Control W0 0x5030 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_30 Peripheral Domain Access Control W0 0x20E88 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_31 Peripheral Domain Access Control W0 0x21F80 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_32 Peripheral Domain Access Control W0 0x23080 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_33 Peripheral Domain Access Control W0 0x24188 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_34 Peripheral Domain Access Control W0 0x25298 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_35 Peripheral Domain Access Control W0 0x263B0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_36 Peripheral Domain Access Control W0 0x274D0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_37 Peripheral Domain Access Control W0 0x285F8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_38 Peripheral Domain Access Control W0 0x29728 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_39 Peripheral Domain Access Control W0 0x2A860 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_4 Peripheral Domain Access Control W0 0x6050 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_40 Peripheral Domain Access Control W0 0x2B9A0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_41 Peripheral Domain Access Control W0 0x2CAE8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_42 Peripheral Domain Access Control W0 0x2DC38 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_43 Peripheral Domain Access Control W0 0x2ED90 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_44 Peripheral Domain Access Control W0 0x2FEF0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_45 Peripheral Domain Access Control W0 0x31058 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_46 Peripheral Domain Access Control W0 0x321C8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_47 Peripheral Domain Access Control W0 0x33340 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_48 Peripheral Domain Access Control W0 0x344C0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_49 Peripheral Domain Access Control W0 0x35648 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_5 Peripheral Domain Access Control W0 0x7078 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_50 Peripheral Domain Access Control W0 0x367D8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_51 Peripheral Domain Access Control W0 0x37970 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_52 Peripheral Domain Access Control W0 0x38B10 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_53 Peripheral Domain Access Control W0 0x39CB8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_54 Peripheral Domain Access Control W0 0x3AE68 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_55 Peripheral Domain Access Control W0 0x3C020 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_56 Peripheral Domain Access Control W0 0x3D1E0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_57 Peripheral Domain Access Control W0 0x3E3A8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_58 Peripheral Domain Access Control W0 0x3F578 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_59 Peripheral Domain Access Control W0 0x40750 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_6 Peripheral Domain Access Control W0 0x80A8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_60 Peripheral Domain Access Control W0 0x41930 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_61 Peripheral Domain Access Control W0 0x42B18 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_62 Peripheral Domain Access Control W0 0x43D08 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_63 Peripheral Domain Access Control W0 0x44F00 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_64 Peripheral Domain Access Control W0 0x46100 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_65 Peripheral Domain Access Control W0 0x47308 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_66 Peripheral Domain Access Control W0 0x48518 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_67 Peripheral Domain Access Control W0 0x49730 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_68 Peripheral Domain Access Control W0 0x4A950 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_69 Peripheral Domain Access Control W0 0x4BB78 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_7 Peripheral Domain Access Control W0 0x90E0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_70 Peripheral Domain Access Control W0 0x4CDA8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_71 Peripheral Domain Access Control W0 0x4DFE0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_72 Peripheral Domain Access Control W0 0x4F220 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_73 Peripheral Domain Access Control W0 0x50468 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_74 Peripheral Domain Access Control W0 0x516B8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_75 Peripheral Domain Access Control W0 0x52910 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_76 Peripheral Domain Access Control W0 0x53B70 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_77 Peripheral Domain Access Control W0 0x54DD8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_78 Peripheral Domain Access Control W0 0x56048 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_79 Peripheral Domain Access Control W0 0x572C0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_8 Peripheral Domain Access Control W0 0xA120 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_80 Peripheral Domain Access Control W0 0x58540 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_81 Peripheral Domain Access Control W0 0x597C8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_82 Peripheral Domain Access Control W0 0x5AA58 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_83 Peripheral Domain Access Control W0 0x5BCF0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_84 Peripheral Domain Access Control W0 0x5CF90 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_85 Peripheral Domain Access Control W0 0x5E238 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_86 Peripheral Domain Access Control W0 0x5F4E8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_87 Peripheral Domain Access Control W0 0x607A0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_88 Peripheral Domain Access Control W0 0x61A60 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_89 Peripheral Domain Access Control W0 0x62D28 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_9 Peripheral Domain Access Control W0 0xB168 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_90 Peripheral Domain Access Control W0 0x63FF8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_91 Peripheral Domain Access Control W0 0x652D0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_92 Peripheral Domain Access Control W0 0x665B0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_93 Peripheral Domain Access Control W0 0x67898 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_94 Peripheral Domain Access Control W0 0x68B88 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_95 Peripheral Domain Access Control W0 0x69E80 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_96 Peripheral Domain Access Control W0 0x6B180 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_97 Peripheral Domain Access Control W0 0x6C488 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_98 Peripheral Domain Access Control W0 0x6D798 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W0_99 Peripheral Domain Access Control W0 0x6EAB0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy. See description for D7ACP . 0 3 read-write D1ACP Domain 1 access control policy. See description for D7ACP . 3 3 read-write D2ACP Domain 2 access control policy. See description for D7ACP . 6 3 read-write D3ACP Domain 3 access control policy. See description for D7ACP . 9 3 read-write D4ACP Domain 4 access control policy. See description for D7ACP . 12 3 read-write D5ACP Domain 5 access control policy. See description for D7ACP . 15 3 read-write D6ACP Domain 6 access control policy. See description for D7ACP . 18 3 read-write D7ACP Domain 7 access control policy 21 3 read-write SE Semaphore enable 30 1 read-write 0 Do not include a semaphore in the DxACP evaluation. #0 1 Include the semaphore defined by W0[SNUM] in the DxACP evaluation. #1 SNUM Semaphore number. Include this hardware semaphore in the DxACP access evaluation. 24 6 read-write PDAC_W1_0 Peripheral Domain Access Control W1 0x2008 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_1 Peripheral Domain Access Control W1 0x3014 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_10 Peripheral Domain Access Control W1 0xC1E8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_100 Peripheral Domain Access Control W1 0x6FF68 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_101 Peripheral Domain Access Control W1 0x71294 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_102 Peripheral Domain Access Control W1 0x725C8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_103 Peripheral Domain Access Control W1 0x73904 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_104 Peripheral Domain Access Control W1 0x74C48 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_105 Peripheral Domain Access Control W1 0x75F94 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_106 Peripheral Domain Access Control W1 0x772E8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_107 Peripheral Domain Access Control W1 0x78644 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_108 Peripheral Domain Access Control W1 0x799A8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_109 Peripheral Domain Access Control W1 0x7AD14 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_11 Peripheral Domain Access Control W1 0xD244 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_110 Peripheral Domain Access Control W1 0x7C088 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_111 Peripheral Domain Access Control W1 0x7D404 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_112 Peripheral Domain Access Control W1 0x7E788 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_113 Peripheral Domain Access Control W1 0x7FB14 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_114 Peripheral Domain Access Control W1 0x80EA8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_115 Peripheral Domain Access Control W1 0x82244 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_116 Peripheral Domain Access Control W1 0x835E8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_117 Peripheral Domain Access Control W1 0x84994 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_118 Peripheral Domain Access Control W1 0x85D48 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_119 Peripheral Domain Access Control W1 0x87104 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_12 Peripheral Domain Access Control W1 0xE2A8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_120 Peripheral Domain Access Control W1 0x884C8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_121 Peripheral Domain Access Control W1 0x89894 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_122 Peripheral Domain Access Control W1 0x8AC68 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_123 Peripheral Domain Access Control W1 0x8C044 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_124 Peripheral Domain Access Control W1 0x8D428 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_125 Peripheral Domain Access Control W1 0x8E814 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_126 Peripheral Domain Access Control W1 0x8FC08 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_127 Peripheral Domain Access Control W1 0x91004 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_128 Peripheral Domain Access Control W1 0x92408 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_129 Peripheral Domain Access Control W1 0x93814 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_13 Peripheral Domain Access Control W1 0xF314 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_130 Peripheral Domain Access Control W1 0x94C28 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_131 Peripheral Domain Access Control W1 0x96044 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_132 Peripheral Domain Access Control W1 0x97468 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_133 Peripheral Domain Access Control W1 0x98894 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_134 Peripheral Domain Access Control W1 0x99CC8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_135 Peripheral Domain Access Control W1 0x9B104 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_136 Peripheral Domain Access Control W1 0x9C548 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_137 Peripheral Domain Access Control W1 0x9D994 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_138 Peripheral Domain Access Control W1 0x9EDE8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_139 Peripheral Domain Access Control W1 0xA0244 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_14 Peripheral Domain Access Control W1 0x10388 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_140 Peripheral Domain Access Control W1 0xA16A8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_141 Peripheral Domain Access Control W1 0xA2B14 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_142 Peripheral Domain Access Control W1 0xA3F88 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_143 Peripheral Domain Access Control W1 0xA5404 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_144 Peripheral Domain Access Control W1 0xA6888 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_145 Peripheral Domain Access Control W1 0xA7D14 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_146 Peripheral Domain Access Control W1 0xA91A8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_147 Peripheral Domain Access Control W1 0xAA644 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_148 Peripheral Domain Access Control W1 0xABAE8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_149 Peripheral Domain Access Control W1 0xACF94 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_15 Peripheral Domain Access Control W1 0x11404 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_150 Peripheral Domain Access Control W1 0xAE448 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_151 Peripheral Domain Access Control W1 0xAF904 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_152 Peripheral Domain Access Control W1 0xB0DC8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_153 Peripheral Domain Access Control W1 0xB2294 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_154 Peripheral Domain Access Control W1 0xB3768 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_155 Peripheral Domain Access Control W1 0xB4C44 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_156 Peripheral Domain Access Control W1 0xB6128 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_157 Peripheral Domain Access Control W1 0xB7614 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_158 Peripheral Domain Access Control W1 0xB8B08 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_159 Peripheral Domain Access Control W1 0xBA004 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_16 Peripheral Domain Access Control W1 0x12488 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_160 Peripheral Domain Access Control W1 0xBB508 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_161 Peripheral Domain Access Control W1 0xBCA14 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_162 Peripheral Domain Access Control W1 0xBDF28 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_163 Peripheral Domain Access Control W1 0xBF444 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_164 Peripheral Domain Access Control W1 0xC0968 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_165 Peripheral Domain Access Control W1 0xC1E94 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_166 Peripheral Domain Access Control W1 0xC33C8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_167 Peripheral Domain Access Control W1 0xC4904 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_168 Peripheral Domain Access Control W1 0xC5E48 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_169 Peripheral Domain Access Control W1 0xC7394 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_17 Peripheral Domain Access Control W1 0x13514 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_170 Peripheral Domain Access Control W1 0xC88E8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_171 Peripheral Domain Access Control W1 0xC9E44 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_172 Peripheral Domain Access Control W1 0xCB3A8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_173 Peripheral Domain Access Control W1 0xCC914 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_174 Peripheral Domain Access Control W1 0xCDE88 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_175 Peripheral Domain Access Control W1 0xCF404 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_176 Peripheral Domain Access Control W1 0xD0988 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_177 Peripheral Domain Access Control W1 0xD1F14 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_178 Peripheral Domain Access Control W1 0xD34A8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_179 Peripheral Domain Access Control W1 0xD4A44 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_18 Peripheral Domain Access Control W1 0x145A8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_180 Peripheral Domain Access Control W1 0xD5FE8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_181 Peripheral Domain Access Control W1 0xD7594 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_182 Peripheral Domain Access Control W1 0xD8B48 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_183 Peripheral Domain Access Control W1 0xDA104 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_184 Peripheral Domain Access Control W1 0xDB6C8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_185 Peripheral Domain Access Control W1 0xDCC94 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_186 Peripheral Domain Access Control W1 0xDE268 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_187 Peripheral Domain Access Control W1 0xDF844 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_188 Peripheral Domain Access Control W1 0xE0E28 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_189 Peripheral Domain Access Control W1 0xE2414 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_19 Peripheral Domain Access Control W1 0x15644 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_190 Peripheral Domain Access Control W1 0xE3A08 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_191 Peripheral Domain Access Control W1 0xE5004 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_192 Peripheral Domain Access Control W1 0xE6608 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_193 Peripheral Domain Access Control W1 0xE7C14 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_194 Peripheral Domain Access Control W1 0xE9228 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_195 Peripheral Domain Access Control W1 0xEA844 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_196 Peripheral Domain Access Control W1 0xEBE68 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_197 Peripheral Domain Access Control W1 0xED494 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_198 Peripheral Domain Access Control W1 0xEEAC8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_199 Peripheral Domain Access Control W1 0xF0104 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_2 Peripheral Domain Access Control W1 0x4028 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_20 Peripheral Domain Access Control W1 0x166E8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_200 Peripheral Domain Access Control W1 0xF1748 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_201 Peripheral Domain Access Control W1 0xF2D94 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_202 Peripheral Domain Access Control W1 0xF43E8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_203 Peripheral Domain Access Control W1 0xF5A44 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_204 Peripheral Domain Access Control W1 0xF70A8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_205 Peripheral Domain Access Control W1 0xF8714 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_206 Peripheral Domain Access Control W1 0xF9D88 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_207 Peripheral Domain Access Control W1 0xFB404 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_208 Peripheral Domain Access Control W1 0xFCA88 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_209 Peripheral Domain Access Control W1 0xFE114 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_21 Peripheral Domain Access Control W1 0x17794 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_210 Peripheral Domain Access Control W1 0xFF7A8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_211 Peripheral Domain Access Control W1 0x100E44 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_212 Peripheral Domain Access Control W1 0x1024E8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_213 Peripheral Domain Access Control W1 0x103B94 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_214 Peripheral Domain Access Control W1 0x105248 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_215 Peripheral Domain Access Control W1 0x106904 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_216 Peripheral Domain Access Control W1 0x107FC8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_217 Peripheral Domain Access Control W1 0x109694 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_218 Peripheral Domain Access Control W1 0x10AD68 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_219 Peripheral Domain Access Control W1 0x10C444 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_22 Peripheral Domain Access Control W1 0x18848 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_220 Peripheral Domain Access Control W1 0x10DB28 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_221 Peripheral Domain Access Control W1 0x10F214 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_222 Peripheral Domain Access Control W1 0x110908 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_223 Peripheral Domain Access Control W1 0x112004 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_224 Peripheral Domain Access Control W1 0x113708 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_225 Peripheral Domain Access Control W1 0x114E14 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_226 Peripheral Domain Access Control W1 0x116528 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_227 Peripheral Domain Access Control W1 0x117C44 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_228 Peripheral Domain Access Control W1 0x119368 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_229 Peripheral Domain Access Control W1 0x11AA94 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_23 Peripheral Domain Access Control W1 0x19904 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_230 Peripheral Domain Access Control W1 0x11C1C8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_231 Peripheral Domain Access Control W1 0x11D904 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_232 Peripheral Domain Access Control W1 0x11F048 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_233 Peripheral Domain Access Control W1 0x120794 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_234 Peripheral Domain Access Control W1 0x121EE8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_235 Peripheral Domain Access Control W1 0x123644 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_236 Peripheral Domain Access Control W1 0x124DA8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_237 Peripheral Domain Access Control W1 0x126514 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_238 Peripheral Domain Access Control W1 0x127C88 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_239 Peripheral Domain Access Control W1 0x129404 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_24 Peripheral Domain Access Control W1 0x1A9C8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_240 Peripheral Domain Access Control W1 0x12AB88 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_241 Peripheral Domain Access Control W1 0x12C314 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_242 Peripheral Domain Access Control W1 0x12DAA8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_243 Peripheral Domain Access Control W1 0x12F244 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_244 Peripheral Domain Access Control W1 0x1309E8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_245 Peripheral Domain Access Control W1 0x132194 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_246 Peripheral Domain Access Control W1 0x133948 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_247 Peripheral Domain Access Control W1 0x135104 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_248 Peripheral Domain Access Control W1 0x1368C8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_249 Peripheral Domain Access Control W1 0x138094 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_25 Peripheral Domain Access Control W1 0x1BA94 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_250 Peripheral Domain Access Control W1 0x139868 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_251 Peripheral Domain Access Control W1 0x13B044 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_252 Peripheral Domain Access Control W1 0x13C828 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_253 Peripheral Domain Access Control W1 0x13E014 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_254 Peripheral Domain Access Control W1 0x13F808 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_255 Peripheral Domain Access Control W1 0x141004 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_256 Peripheral Domain Access Control W1 0x142808 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_26 Peripheral Domain Access Control W1 0x1CB68 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_27 Peripheral Domain Access Control W1 0x1DC44 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_28 Peripheral Domain Access Control W1 0x1ED28 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_29 Peripheral Domain Access Control W1 0x1FE14 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_3 Peripheral Domain Access Control W1 0x5044 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_30 Peripheral Domain Access Control W1 0x20F08 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_31 Peripheral Domain Access Control W1 0x22004 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_32 Peripheral Domain Access Control W1 0x23108 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_33 Peripheral Domain Access Control W1 0x24214 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_34 Peripheral Domain Access Control W1 0x25328 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_35 Peripheral Domain Access Control W1 0x26444 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_36 Peripheral Domain Access Control W1 0x27568 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_37 Peripheral Domain Access Control W1 0x28694 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_38 Peripheral Domain Access Control W1 0x297C8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_39 Peripheral Domain Access Control W1 0x2A904 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_4 Peripheral Domain Access Control W1 0x6068 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_40 Peripheral Domain Access Control W1 0x2BA48 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_41 Peripheral Domain Access Control W1 0x2CB94 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_42 Peripheral Domain Access Control W1 0x2DCE8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_43 Peripheral Domain Access Control W1 0x2EE44 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_44 Peripheral Domain Access Control W1 0x2FFA8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_45 Peripheral Domain Access Control W1 0x31114 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_46 Peripheral Domain Access Control W1 0x32288 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_47 Peripheral Domain Access Control W1 0x33404 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_48 Peripheral Domain Access Control W1 0x34588 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_49 Peripheral Domain Access Control W1 0x35714 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_5 Peripheral Domain Access Control W1 0x7094 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_50 Peripheral Domain Access Control W1 0x368A8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_51 Peripheral Domain Access Control W1 0x37A44 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_52 Peripheral Domain Access Control W1 0x38BE8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_53 Peripheral Domain Access Control W1 0x39D94 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_54 Peripheral Domain Access Control W1 0x3AF48 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_55 Peripheral Domain Access Control W1 0x3C104 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_56 Peripheral Domain Access Control W1 0x3D2C8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_57 Peripheral Domain Access Control W1 0x3E494 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_58 Peripheral Domain Access Control W1 0x3F668 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_59 Peripheral Domain Access Control W1 0x40844 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_6 Peripheral Domain Access Control W1 0x80C8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_60 Peripheral Domain Access Control W1 0x41A28 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_61 Peripheral Domain Access Control W1 0x42C14 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_62 Peripheral Domain Access Control W1 0x43E08 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_63 Peripheral Domain Access Control W1 0x45004 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_64 Peripheral Domain Access Control W1 0x46208 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_65 Peripheral Domain Access Control W1 0x47414 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_66 Peripheral Domain Access Control W1 0x48628 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_67 Peripheral Domain Access Control W1 0x49844 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_68 Peripheral Domain Access Control W1 0x4AA68 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_69 Peripheral Domain Access Control W1 0x4BC94 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_7 Peripheral Domain Access Control W1 0x9104 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_70 Peripheral Domain Access Control W1 0x4CEC8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_71 Peripheral Domain Access Control W1 0x4E104 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_72 Peripheral Domain Access Control W1 0x4F348 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_73 Peripheral Domain Access Control W1 0x50594 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_74 Peripheral Domain Access Control W1 0x517E8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_75 Peripheral Domain Access Control W1 0x52A44 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_76 Peripheral Domain Access Control W1 0x53CA8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_77 Peripheral Domain Access Control W1 0x54F14 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_78 Peripheral Domain Access Control W1 0x56188 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_79 Peripheral Domain Access Control W1 0x57404 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_8 Peripheral Domain Access Control W1 0xA148 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_80 Peripheral Domain Access Control W1 0x58688 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_81 Peripheral Domain Access Control W1 0x59914 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_82 Peripheral Domain Access Control W1 0x5ABA8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_83 Peripheral Domain Access Control W1 0x5BE44 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_84 Peripheral Domain Access Control W1 0x5D0E8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_85 Peripheral Domain Access Control W1 0x5E394 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_86 Peripheral Domain Access Control W1 0x5F648 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_87 Peripheral Domain Access Control W1 0x60904 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_88 Peripheral Domain Access Control W1 0x61BC8 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_89 Peripheral Domain Access Control W1 0x62E94 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_9 Peripheral Domain Access Control W1 0xB194 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_90 Peripheral Domain Access Control W1 0x64168 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_91 Peripheral Domain Access Control W1 0x65444 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_92 Peripheral Domain Access Control W1 0x66728 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_93 Peripheral Domain Access Control W1 0x67A14 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_94 Peripheral Domain Access Control W1 0x68D08 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_95 Peripheral Domain Access Control W1 0x6A004 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_96 Peripheral Domain Access Control W1 0x6B308 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_97 Peripheral Domain Access Control W1 0x6C614 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_98 Peripheral Domain Access Control W1 0x6D928 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PDAC_W1_99 Peripheral Domain Access Control W1 0x6EC44 32 read-write n 0x0 0x0 D10ACP Domain 10 access control policy. See description for D7ACP . 6 3 read-write D11ACP Domain 11 access control policy. See description for D7ACP . 9 3 read-write D12ACP Domain 12 access control policy. See description for D7ACP . 12 3 read-write D13ACP Domain 13 access control policy. See description for D7ACP . 15 3 read-write D14ACP Domain 14 access control policy. See description for D7ACP . 18 3 read-write D15ACP Domain 15 access control policy. See description for D7ACP . 21 3 read-write D8ACP Domain 8 access control policy. See description for D7ACP . 0 3 read-write D9ACP Domain 9 access control policy. See description for D7ACP . 3 3 read-write LK2 Lock 29 2 read-write 00 Entire PDACn can be written. #00 01 Entire PDACn can be written. #01 10 Domain "x" can only update the DxACP field; no other PDACn fields can be written. #10 11 PDACn is locked (read-only) until the next reset. #11 VLD Valid 31 1 read-write 0 The PDACn assignment is invalid. #0 1 The PDACn assignment is valid. #1 PID0 Process Identifier 0xE00 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID1 Process Identifier 0x1504 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID10 Process Identifier 0x54DC 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID11 Process Identifier 0x5C08 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID12 Process Identifier 0x6338 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID13 Process Identifier 0x6A6C 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID14 Process Identifier 0x71A4 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID15 Process Identifier 0x78E0 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID16 Process Identifier 0x8020 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID17 Process Identifier 0x8764 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID18 Process Identifier 0x8EAC 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID19 Process Identifier 0x95F8 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID2 Process Identifier 0x1C0C 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID20 Process Identifier 0x9D48 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID21 Process Identifier 0xA49C 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID22 Process Identifier 0xABF4 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID23 Process Identifier 0xB350 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID24 Process Identifier 0xBAB0 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID25 Process Identifier 0xC214 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID26 Process Identifier 0xC97C 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID27 Process Identifier 0xD0E8 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID28 Process Identifier 0xD858 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID29 Process Identifier 0xDFCC 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID3 Process Identifier 0x2318 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID30 Process Identifier 0xE744 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID31 Process Identifier 0xEEC0 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID32 Process Identifier 0xF640 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID33 Process Identifier 0xFDC4 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID34 Process Identifier 0x1054C 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID35 Process Identifier 0x10CD8 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID36 Process Identifier 0x11468 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID4 Process Identifier 0x2A28 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID5 Process Identifier 0x313C 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID6 Process Identifier 0x3854 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID7 Process Identifier 0x3F70 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID8 Process Identifier 0x4690 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write PID9 Process Identifier 0x4DB4 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write 00 Register can be written by any secure privileged write. #00 01 Register can be written by any secure privileged write. #01 10 Register can only be written by a secure privileged write from bus master n. #10 11 Register is locked (read-only) until the next reset. #11 PID Process identifier 0 6 read-write TSM Three-state model 28 1 read-write